Searched refs:CSR_MSTATUS (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh329 CSR_MSTATUS = 0x300, enumerator in enum:RiscvISA::CSRIndex
500 {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
728 {CSR_MSTATUS, MSTATUS_MASK},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h796 #define CSR_MSTATUS 0x300 macro
1288 DECLARE_CSR(mstatus, CSR_MSTATUS)

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