Searched refs:CSR_MIP (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh340 CSR_MIP = 0x344, enumerator in enum:RiscvISA::CSRIndex
511 {CSR_MIP, {"mip", MISCREG_IP}},
731 {CSR_MIP, MI_MASK}
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h807 #define CSR_MIP 0x344 macro
1299 DECLARE_CSR(mip, CSR_MIP)

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