Searched refs:CSR_MIE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh333 CSR_MIE = 0x304, enumerator in enum:RiscvISA::CSRIndex
504 {CSR_MIE, {"mie", MISCREG_IE}},
730 {CSR_MIE, MI_MASK},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h800 #define CSR_MIE 0x304 macro
1292 DECLARE_CSR(mie, CSR_MIE)

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