Searched refs:CSR_MHPMEVENT21 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh411 CSR_MHPMEVENT21 = 0x335, enumerator in enum:RiscvISA::CSRIndex
581 {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h884 #define CSR_MHPMEVENT21 0x335 macro
1376 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)

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