Searched refs:CSR_MHPMEVENT15 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh405 CSR_MHPMEVENT15 = 0x32F, enumerator in enum:RiscvISA::CSRIndex
575 {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h878 #define CSR_MHPMEVENT15 0x32f macro
1370 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)

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