Searched refs:CSR_MHPMEVENT14 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh404 CSR_MHPMEVENT14 = 0x32E, enumerator in enum:RiscvISA::CSRIndex
574 {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h877 #define CSR_MHPMEVENT14 0x32e macro
1369 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)

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