Searched refs:CSR_MHPMEVENT13 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh403 CSR_MHPMEVENT13 = 0x32D, enumerator in enum:RiscvISA::CSRIndex
573 {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h876 #define CSR_MHPMEVENT13 0x32d macro
1368 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)

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