Searched refs:CSR_MHPMEVENT12 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh402 CSR_MHPMEVENT12 = 0x32C, enumerator in enum:RiscvISA::CSRIndex
572 {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h875 #define CSR_MHPMEVENT12 0x32c macro
1367 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)

Completed in 18 milliseconds