Searched refs:CSR_MHPMCOUNTER31 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh391 CSR_MHPMCOUNTER31 = 0xC1F, enumerator in enum:RiscvISA::CSRIndex
562 {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h865 #define CSR_MHPMCOUNTER31 0xb1f macro
1357 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)

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