Searched refs:CSR_MHPMCOUNTER28 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh388 CSR_MHPMCOUNTER28 = 0xC1C, enumerator in enum:RiscvISA::CSRIndex
559 {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h862 #define CSR_MHPMCOUNTER28 0xb1c macro
1354 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)

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