Searched refs:CSR_MHPMCOUNTER18 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh378 CSR_MHPMCOUNTER18 = 0xC12, enumerator in enum:RiscvISA::CSRIndex
549 {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h852 #define CSR_MHPMCOUNTER18 0xb12 macro
1344 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)

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