Searched refs:CSR_MCYCLE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh361 CSR_MCYCLE = 0xB00, enumerator in enum:RiscvISA::CSRIndex
532 {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h835 #define CSR_MCYCLE 0xb00 macro
1327 DECLARE_CSR(mcycle, CSR_MCYCLE)

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