Searched refs:CSR_HPMCOUNTER27 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh305 CSR_HPMCOUNTER27 = 0xC1B, enumerator in enum:RiscvISA::CSRIndex
477 {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h781 #define CSR_HPMCOUNTER27 0xc1b macro
1273 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)

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