Searched refs:when (Results 51 - 75 of 99) sorted by relevance

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/gem5/src/gpu-compute/
H A Dshader.hh168 void ScheduleAdd(uint32_t *val, Tick when, int x);
H A Dlds_state.hh137 schedule(Tick when) argument
139 mainEventQueue[0]->schedule(this, when);
212 // wavefronts are launched, the counter goes up for that workgroup and when
215 // transition, not whenever the counter is 0 as it always starts with 0 when
H A Dshader.cc315 Shader::ScheduleAdd(uint32_t *val,Tick when,int x) argument
318 sa_when.push_back(tick_cnt + when);
393 // even when the perLaneTLB flag is turned on
H A Dcompute_unit.hh225 uint64_t when,
228 timestampVec.push_back(when);
234 timestampVec.push_back(when);
349 // when the instruction is committed, this number is still incremented by 1
370 // flag per vector SIMD unit that is set when there is at least one
222 registerEvent(uint32_t simdId, uint32_t regIdx, uint32_t operandSize, uint64_t when, uint8_t newStatus) argument
/gem5/src/python/pybind11/
H A Devent.cc123 }, py::arg("event"), py::arg("when"))
164 .def("when", &Event::when)
/gem5/src/dev/
H A Dmc146818.cc180 // happens after 0.5s when the divider chain goes
282 Tick rtcTimerInterruptTickOffset = event.when() - curTick();
284 Tick rtcClockTickOffset = tickEvent.when() - curTick();
H A Dintel_8254_timer.cc245 event_tick_offset = event.when() - curTick();
315 return (when() - curTick() + interval - 1) / interval;
/gem5/src/dev/serial/
H A Duart8250.cc269 // if the kernel wants an interrupt when we have data
296 rxintrwhen = rxIntrEvent.when();
301 txintrwhen = txIntrEvent.when();
/gem5/src/cpu/trace/
H A Dtrace_cpu.cc204 // If the replay is configured to exit early, that is when any one
406 // index in the ROB and register dependency arrays. Thus, when we reach
686 // If it fails, return the packet to retry when a retry is signalled by
933 // A store is considered complete when a request is sent, thus ROB entry is
935 // is received. A load is considered complete when a response is received,
944 // when node is executed and taken off from readyList.
1173 // If it fails, save the packet to retry when a retry is signalled by
1201 TraceCPU::schedDcacheNextEvent(Tick when) argument
1205 when);
1206 schedule(dcacheNextEvent, when);
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/gem5/src/dev/net/
H A Dsinic.cc461 Tick when = curTick(); local
463 when += intrDelay;
464 cpuIntrPost(when);
503 Base::cpuIntrPost(Tick when) argument
514 assert(when >= curTick());
522 if (when > intrTick && intrTick != 0) {
528 intrTick = when;
1246 intrEventTick = intrEvent->when();
1385 Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
H A Ddist_iface.cc265 // The receive thread must finish when simulation is about to exit
362 inform("Dist sync scheduled at %lu and repeats %lu\n", when(),
435 // This is called from the receiver thread when it starts running. The new
467 // Schedule pending packets asap in case link speed/delay changed when
510 assert(send_tick > master->syncEvent->when() -
513 assert(send_tick + send_delay + linkDelay > master->syncEvent->when());
538 // Note : this is called from the simulation thread when a receive done
540 // the event queue queue lock when this is called!
868 // At this point, we have no clue when everyone will reach the sync
870 // Dist-gem5 will reactivate all thread contexts when everyon
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H A Ddist_etherlink.cc222 Tick event_time = event->when();
H A Dns_gige.cc778 Tick when = curTick(); local
780 when += intrDelay;
782 cpuIntrPost(when);
846 NSGigE::cpuIntrPost(Tick when) argument
857 assert(when >= curTick());
859 if (when > intrTick && intrTick != 0) {
865 intrTick = when;
1086 // exit the loop. however, when the DMA is done it will trigger
2166 Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
2187 intrEventTick = intrEvent->when();
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/gem5/src/systemc/core/
H A Devent.cc181 if (scheduler.delayed(t) >= delayedNotify.when())
/gem5/src/dev/arm/
H A Denergy_ctrl.cc227 Tick next_event = updateAckEvent.scheduled() ? updateAckEvent.when() : 0;
H A Dpl111.cc514 warn("CLCD controller buffer underrun, took %d ticks when should"
538 // schedule the next read based on when the last frame started
625 read_event_time = readEvent.when();
627 fill_fifo_event_time = fillFifoEvent.when();
629 int_event_time = intEvent.when();
639 dmaDoneEventAll[x].when() : 0;
H A Drtc_pl031.cc144 break; // Can't stop when started
213 event_time = matchEvent.when();
H A Dgic_v2.hh114 /** Mask off SGI's when setting/clearing pending bits */
426 void postInt(uint32_t cpu, Tick when);
427 void postFiq(uint32_t cpu, Tick when);
H A Dvgic.cc270 // Maintenance interrupt -- via eisr -- is flagged when
364 VGic::postVInt(uint32_t cpu, Tick when)
368 eventq->schedule(postVIntEvent[cpu], when);
464 interrupt_time[cpu] = postVIntEvent[cpu]->when();
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Ddirty.S63 # Make sure that superpage entries trap when PPN LSBs are set.
/gem5/util/systemc/gem5_within_systemc/
H A Dsc_module.cc95 Module::SCEventQueue::wakeup(Tick when) argument
98 /* Don't bother to use 'when' for now */
/gem5/src/cpu/
H A Dexetrace.cc68 ccprintf(outs, "%7d: ", when);
196 * microops aren't printed, then it's printed only when the final microop
198 * complete/print when they fault.
/gem5/src/dev/storage/
H A Dide_disk.cc1089 reschedule = dmaTransferEvent.when();
1094 reschedule = dmaReadWaitEvent.when();
1099 reschedule = dmaWriteWaitEvent.when();
1104 reschedule = dmaPrdReadEvent.when();
1109 reschedule = dmaReadEvent.when();
1114 reschedule = dmaWriteEvent.when();
/gem5/configs/common/
H A DSimulation.py125 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken>
126 2. cpt.<some number, usually the tick value when the checkpoint was taken>
233 when, period = options.take_checkpoints.split(",", 1)
234 when = int(when)
238 exit_event = m5.simulate(when - m5.curTick())
241 exit_event = m5.simulate(when - m5.curTick())
248 sim_ticks = when
363 # (when warmup period longer than starting point)
445 fatal("Must specify --caches when usin
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/gem5/src/arch/sparc/
H A Disa.cc173 panic("Tick comparison event active when clearing the ISA object.\n");
349 DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
704 tick_cmp = tickCompare->when();
706 stick_cmp = sTickCompare->when();
708 hstick_cmp = hSTickCompare->when();

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