/gem5/src/systemc/tests/systemc/misc/parsing/T_1_1_2_3/ |
H A D | T_1_1_2_3.cpp | 49 int state; local
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/gem5/src/cpu/minor/ |
H A D | fetch1.cc | 138 fetchInfo[tid].state == FetchRunning) { 150 /* Reference the currently used thread state. */ 180 request->state = FetchRequest::InTranslation; 211 operator <<(std::ostream &os, Fetch1::IcacheState state) argument 213 switch (state) { 221 os << "IcacheState-" << static_cast<int>(state); 245 state = Translated; 271 response->state = FetchRequest::Translated; 291 if (request->state == FetchRequest::InTranslation) { 301 request->state 469 operator <<(std::ostream &os, Fetch1::FetchState state) argument [all...] |
H A D | lsq.cc | 72 state(NotIssued) 158 return state == StoreToStoreBuffer; 164 DPRINTFS(MinorMem, (&port), "Setting state from %d to %d for request:" 165 " %s\n", state, new_state, *inst); 166 state = new_state; 172 /* @todo, There is currently only one 'completed' state. This 174 return state == Complete; 182 os << ';' << state; local 206 operator <<(std::ostream &os, LSQ::LSQRequest::LSQRequestState state) argument 208 switch (state) { 1728 operator <<(std::ostream &os, LSQ::MemoryState state) argument [all...] |
/gem5/src/systemc/tests/systemc/kernel/process_control/test02/ |
H A D | test02.cpp | 78 static int state = 0; local 79 switch ( state ) 84 << "," << state << ") initialization call " << endl; 85 state = 1; 91 << "," << state << ") after wait on m_clk.posedge() " << endl;
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/gem5/ext/testlib/ |
H A D | handlers.py | 47 import state 127 if record['status'] in (state.Status.Complete, state.Status.Avoided): 192 state.Result.Errored: color.Red, 193 state.Result.Failed: color.Red, 194 state.Result.Passed: color.Green, 195 state.Result.Skipped: color.Cyan, 209 if record['status'] == state.Status.Building: 214 if result in (state.Result.Skipped, state [all...] |
H A D | result.py | 35 import state 62 return self._metadata.result.value != state.Result.Passed 208 state.Result.Errored: 'errors', 209 state.Result.Failed: 'failures', 210 state.Result.Passed: 'tests' 231 state.Result.Errored: 'errors', 232 state.Result.Failed: 'failures', 233 state.Result.Passed: 'tests', 234 state.Result.Skipped: 'skipped'
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/gem5/src/systemc/tests/systemc/kernel/process_control/test03/ |
H A D | test03.cpp | 91 static int state = 0; local 92 switch( state ) 104 state = 1; 111 static int state = 0; local 112 switch( state ) 124 state = 1; 131 static int state = 0; local 132 switch( state ) 143 state = 1;
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/gem5/src/dev/ |
H A D | dma_device.cc | 70 // should always see a response with a sender state 73 // get the DMA sender state 74 DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState); local 75 assert(state); 80 state->numBytes, state->totBytes, 81 state->completionEvent ? 82 state->completionEvent->scheduled() : 0); 89 state->numBytes += pkt->req->getSize(); 90 assert(state [all...] |
/gem5/src/mem/ |
H A D | xbar.cc | 136 port(_port), xbar(_xbar), _name(_name), state(IDLE), 144 // ensure the state is busy at this point, as the layer should 148 assert(state == BUSY); 165 // if we are in the retry state, we will not see anything but the 168 // this state again in zero time if the peer does not immediately 174 if (state == BUSY || waitingForPeer != NULL) { 187 state = BUSY; 198 assert(state == BUSY); 220 assert(state == BUSY); 231 assert(state [all...] |
/gem5/ext/ply/ply/ |
H A D | lex.py | 124 self.lexstate = "INITIAL" # Current lexer state 127 self.lexstateignore = {} # Dictionary of ignored characters for each state 128 self.lexstateerrorf = {} # Dictionary of error functions for each state 185 # Collect all functions in the initial state 261 # begin() - Changes the lexing state 263 def begin(self,state): 264 if not state in self.lexstatere: 265 raise ValueError("Undefined state") 266 self.lexre = self.lexstatere[state] 267 self.lexretext = self.lexstateretext[state] [all...] |
H A D | yacc.py | 314 # Set up the state and symbol stacks 324 # The start state is assumed to be (0,$end) 330 state = 0 338 debug.debug('State : %s', state) 357 t = actions[state].get(ltype) 363 state = t 366 debug.debug("Action : Shift and goto state %s", t) 389 debug.info("Action : Reduce rule [%s] with %s and goto state %d", p.str, "["+",".join([format_stack_entry(_v.value) for _v in symstack[-plen:]])+"]",-t) 391 debug.info("Action : Reduce rule [%s] with %s and goto state %d", p.str, [],-t) 426 state [all...] |
/gem5/src/dev/arm/ |
H A D | RealView.py | 129 def generateDeviceTree(self, state): 151 state.addrCells(self.conf_base) + 152 state.sizeCells(self.conf_size) )) 162 ranges += state.addrCells(self.pci_pio_base) 167 ranges += state.addrCells(0x40000000) # Fixed offset 173 int_phandle = state.phandle(gic) 215 def generateDeviceTree(self, state): 219 state.addrCells(self.pio_addr) + 220 state.sizeCells(0x1000) )) 249 def generateDeviceTree(self, state) [all...] |
/gem5/src/mem/slicc/ast/ |
H A D | StateDeclAST.py | 60 for state in self.states: 61 state.generate(t)
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/gem5/ext/nomali/lib/ |
H A D | nomali_api.cc | 58 nomali_error_t intState(int *state, nomali_int_t intno) const; 179 NoMaliApi::intState(int *state, nomali_int_t intno) const argument 181 if (!state) 186 *state = _gpu->intGPUAsserted(); 190 *state = _gpu->intJobAsserted(); 194 *state = _gpu->intMMUAsserted(); 364 nomali_int_state(nomali_handle_t h, int *state, argument 368 return gpu ? gpu->intState(state, intno) : NOMALI_E_HANDLE;
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/gem5/src/sim/ |
H A D | drain.hh | 52 * An object starts out in the Running state. When the simulator 55 * or Drained state. If any object enters the Draining state 57 * all objects have entered the Drained state. 60 * transfer the object to the Running state. This in turn results in a 63 * such cases, the new objects will be created in the Resuming state 66 * \note Even though the state of an object (visible to the rest of 68 * if all objects have entered the Drained state, the protocol is 75 Resuming, /** Transient state while the simulator is resuming */ 83 * state befor 143 DrainState state() const { return _state; } function in class:DrainManager [all...] |
/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | OutputUnit.hh | 79 set_vc_state(VC_state_type state, int vc, Cycles curTime) argument 81 m_outvc_state[vc]->setState(state, curTime); 109 std::vector<OutVcState *> m_outvc_state; // vc state of downstream router
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/gem5/src/cpu/simple/ |
H A D | timing.cc | 453 WholeTranslationState *state = 457 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 459 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 464 WholeTranslationState *state = 467 = new DataTranslation<TimingSimpleCPU *>(this, state); 543 WholeTranslationState *state = 546 new DataTranslation<TimingSimpleCPU *>(this, state, 0); 548 new DataTranslation<TimingSimpleCPU *>(this, state, 1); 553 WholeTranslationState *state = 556 new DataTranslation<TimingSimpleCPU *>(this, state); [all...] |
/gem5/src/arch/x86/ |
H A D | decoder.cc | 76 //This function drives the decoder state machine. 84 if (state == ResetState) 85 state = doResetState(); 86 if (state == FromCacheState) { 87 state = doFromCacheState(); 95 switch (state) { 97 state = doPrefixState(nextByte); 100 state = doVex2Of2State(nextByte); 103 state = doVex2Of3State(nextByte); 106 state [all...] |
H A D | pagetable_walker.cc | 161 // undo the adding of the sender state and delete it, as we 183 assert(state == Ready); 235 nextState = state; 236 state = Waiting; 245 state = nextState; 250 state = Ready; 271 state = nextState; 283 assert(state != Ready && state != Waiting); 298 switch(state) { [all...] |
/gem5/src/mem/cache/prefetch/ |
H A D | access_map_pattern_matching.cc | 120 Addr block, enum AccessMapState state) 123 entry.states[block] = state; 126 if (state == AM_INIT) return; 130 if (state == AM_PREFETCH) { 132 } else if (state == AM_ACCESS) { 137 if (state == AM_ACCESS) { 143 if (state == AM_ACCESS) { 119 setEntryState(AccessMapEntry &entry, Addr block, enum AccessMapState state) argument
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/gem5/src/mem/slicc/symbols/ |
H A D | StateMachine.py | 102 def addState(self, state): 104 self.states[state.ident] = state 182 index = (trans.state, trans.event) 317 void countTransition(${ident}_State state, ${ident}_Event event); 318 void possibleTransition(${ident}_State state, ${ident}_Event event); 320 bool isPossible(${ident}_State state, ${ident}_Event event); 321 uint64_t getTransitionCount(${ident}_State state, ${ident}_Event event); 351 ${ident}_State state, 548 for (int state [all...] |
/gem5/ext/pybind11/tests/ |
H A D | test_enum.py | 183 state = m.Flags.Read | m.Flags.Write 184 assert (state & m.Flags.Read) != 0 185 assert (state & m.Flags.Write) != 0 186 assert (state & m.Flags.Execute) == 0 187 assert (state & 1) == 0 189 state2 = ~state 191 assert int(state ^ state2) == -1
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H A D | test_virtual_functions.cpp | 18 ExampleVirt(int state) : state(state) { print_created(this, state); } argument 19 ExampleVirt(const ExampleVirt &e) : state(e.state) { print_copy_created(this); } 20 ExampleVirt(ExampleVirt &&e) : state(e.state) { print_move_created(this); e.state = 0; } 25 "ExampleVirt::run(state 39 int state; member in class:ExampleVirt [all...] |
/gem5/configs/boot/ |
H A D | natbox-netperf.rcS | 42 $IPTABLES -A FORWARD -i $EXTIF -o $INTIF -m state --state ESTABLISHED,RELATED -j ACCEPT
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/gem5/src/dev/i2c/ |
H A D | bus.hh | 86 enum I2CState state; member in class:I2CBus
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