Searched refs:fatal (Results 201 - 220 of 220) sorted by relevance
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| /gem5/src/sim/ |
| H A D | pseudo_inst.cc | 336 fatal("file error: Can't open symbol table file %s\n", filename);
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| H A D | syscall_emul.cc | 69 fatal("syscall %s (#%d) unimplemented.", desc->name(), callnum);
464 fatal("readlink('/proc/self/exe') unable to resolve path to "
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| H A D | syscall_emul.hh | 1558 fatal("temp_pid is too large: %d", temp_pid);
1846 // fatal and bail out of the simulation.
1868 fatal("mmap: cannot stat file");
2186 * a fatal check in Process constructor). The execve call is supposed to
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| /gem5/src/cpu/ |
| H A D | base.cc | 262 fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
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| /gem5/src/gpu-compute/ |
| H A D | compute_unit.hh | 714 fatal("an LDS port was already allocated");
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| H A D | compute_unit.cc | 140 fatal("Invalid WF execution policy (CU)\n");
766 fatal("pkt is not a read nor a write\n");
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| H A D | gpu_tlb.cc | 793 fatal("GpuTLB doesn't support full-system mode\n");
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| /gem5/src/cpu/simple/ |
| H A D | atomic.cc | 220 fatal("The atomic CPU requires the memory system to be in "
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| H A D | timing.cc | 203 fatal("The timing CPU requires the memory system to be in "
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| /gem5/src/cpu/o3/ |
| H A D | cpu.cc | 368 fatal("FullO3CPU %s has no interrupt controller.\n"
1162 fatal("The O3 CPU requires the memory system to be in "
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| H A D | rename_impl.hh | 73 fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
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| H A D | commit_impl.hh | 101 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
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| /gem5/src/systemc/core/ |
| H A D | sc_module.cc | 121 fatal("%s does not have any port named %s\n", name(), if_name);
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3.cc | 723 fatal("Master port is not connected.\n");
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| H A D | ufs_device.cc | 758 fatal("Number of UFS command slots should be between 1 and 32.");
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| /gem5/src/mem/cache/ |
| H A D | base.cc | 184 fatal("Cache ports on %s are not connected\n", name());
1870 fatal("Restoring from checkpoints with dirty caches is not "
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| /gem5/src/python/m5/ |
| H A D | SimObject.py | 1586 fatal("%s.%s without default or user set value",
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| /gem5/src/arch/sparc/ |
| H A D | tlb.cc | 61 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
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| /gem5/src/arch/arm/linux/ |
| H A D | process.cc | 88 fatal("gem5 does not support ARM OABI binaries. Please recompile "
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| /gem5/src/arch/arm/ |
| H A D | table_walker.cc | 124 fatal("Cannot access table walker port through stage-two walker\n");
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Completed in 106 milliseconds
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