Searched refs:Tick (Results 226 - 250 of 407) sorted by relevance
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/gem5/src/dev/arm/ |
H A D | timer_cpulocal.hh | 182 Tick read(PacketPtr pkt) override; 189 Tick write(PacketPtr pkt) override;
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H A D | gic_v3.hh | 121 Tick read(PacketPtr pkt) override; 127 Tick write(PacketPtr pkt) override;
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H A D | timer_a9global.cc | 65 Tick 82 A9GlobalTimer::Timer::getTimeCounterFromTicks(Tick ticks) 145 Tick 218 Tick time = parent->clockPeriod() * (control.prescalar + 1) * (cmpVal + 1); 272 Tick event_time; 296 Tick event_time;
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H A D | rv_ctrl.cc | 55 Tick 70 Tick clk; 75 Tick clk100; 131 Tick 273 RealViewOsc::clockPeriod(Tick clock_period)
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H A D | generic_timer.hh | 68 Tick _period; 69 /// Tick when the counter was reset. 70 Tick _resetTick; 95 Tick period() const { return _period; } 307 Tick read(PacketPtr pkt) override; 308 Tick write(PacketPtr pkt) override;
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H A D | rv_ctrl.hh | 175 Tick read(PacketPtr pkt) override; 182 Tick write(PacketPtr pkt) override; 220 void clockPeriod(Tick clock_period);
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/gem5/src/mem/cache/ |
H A D | mshr_queue.cc | 62 Tick when_ready, Counter order, bool alloc_on_fill) 88 MSHRQueue::delay(MSHR *mshr, Tick delay_ticks)
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H A D | mshr.hh | 158 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 270 * @param readTime Tick at which the packet is processed by this cache 276 void add(PacketPtr pkt, Tick readyTime, Counter order, 421 Tick when_ready, Counter _order, bool alloc_on_fill); 436 void allocateTarget(PacketPtr target, Tick when, Counter order, 515 void delay(Tick delay_ticks)
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H A D | noncoherent_cache.cc | 101 NoncoherentCache::doWritebacks(PacketList& writebacks, Tick forward_time) 123 Tick forward_time, Tick request_time) 222 Tick 260 Tick completion_time;
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/gem5/src/dev/net/ |
H A D | etherswitch.cc | 129 uint64_t outputBufferSize, Tick delay, 130 Tick delay_var, double rate, unsigned id) 202 Tick 205 Tick delay = (Tick)ceil(((double)outputFifo.front()->simLength 208 delay += random_mt.random<Tick>(0, delayVar); 283 Tick event_time = txEvent.when(); 296 Tick event_time;
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H A D | i8254xGBe.hh | 89 Tick fetchDelay, wbDelay; 90 Tick fetchCompDelay, wbCompDelay; 91 Tick rxWriteDelay, txReadDelay; 166 Tick intClock() { return SimClock::Int::ns * 1024; } 525 Tick lastInterrupt; 527 Tick read(PacketPtr pkt) override; 528 Tick write(PacketPtr pkt) override; 530 Tick writeConfig(PacketPtr pkt) override;
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.hh | 219 * @param when Tick at which to schedule event 221 void schedDcacheNextEvent(Tick when); 363 Tick tick; 447 * @return Tick when first packet must be sent 449 Tick init(); 691 Tick execTick; 880 * @return Tick when first packet must be sent 882 Tick init(); 890 void adjustInitTraceOffset(Tick& offset); 951 void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tic [all...] |
/gem5/src/cpu/ |
H A D | thread_state.cc | 74 Tick quiesceEndTick = 0; 93 Tick quiesceEndTick;
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/gem5/src/learning_gem5/part2/ |
H A D | simple_cache.hh | 109 Tick recvAtomic(PacketPtr pkt) override 291 Tick missTime;
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/gem5/src/dev/x86/ |
H A D | cmos.cc | 47 Tick 66 Tick
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/gem5/src/dev/ |
H A D | mc146818.cc | 95 bool bcd, Tick frequency) 282 Tick rtcTimerInterruptTickOffset = event.when() - curTick(); 284 Tick rtcClockTickOffset = tickEvent.when() - curTick(); 304 Tick rtcTimerInterruptTickOffset; 307 Tick rtcClockTickOffset; 312 MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
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/gem5/src/gpu-compute/ |
H A D | lds_state.hh | 124 Tick nextTick = 0; 137 schedule(Tick when) 166 virtual Tick 230 std::queue<std::pair<Tick, PacketPtr>> returnQueue; 381 returnQueuePush(std::pair<Tick, PacketPtr> thePair); 383 Tick
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H A D | lds_state.cc | 215 Tick processingTime = 220 Tick doneAt = earliestReturnTime() + processingTime; 229 LdsState::returnQueuePush(std::pair<Tick, PacketPtr> thePair) 279 Tick now = clockEdge(); 309 Tick next = returnQueue.front().first;
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/gem5/src/cpu/kvm/ |
H A D | base.cc | 179 Tick 183 Tick delay = sendAtomic(pkt); 619 Tick delay(0); 638 const Tick ticksToExecute( 708 Tick 728 Tick 729 BaseKvmCPU::kvmRun(Tick ticks) 731 Tick ticksExecuted; 990 Tick 1009 Tick tick [all...] |
/gem5/src/mem/ |
H A D | bridge.cc | 136 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay; 190 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay; 216 Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when) 233 Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when) 340 Tick
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H A D | coherent_xbar.cc | 175 Tick old_header_delay = pkt->headerDelay; 178 Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod(); 184 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay; 430 Tick response_time = clockEdge() + pkt->headerDelay; 469 Tick xbar_delay = responseLatency * clockPeriod(); 475 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay; 484 Tick latency = pkt->headerDelay; 615 Tick xbar_delay = 623 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay; 668 Tick latenc [all...] |
/gem5/src/sim/ |
H A D | dvfs_handler.cc | 153 Tick when = curTick() + _transLatency; 211 std::vector<Tick> whens; 241 std::vector<Tick> whens;
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/gem5/src/cpu/o3/ |
H A D | dyn_inst_impl.hh | 73 Tick fetch = this->fetchTick; 76 Tick val; 97 Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
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/gem5/src/dev/pci/ |
H A D | host.hh | 282 Tick read(PacketPtr pkt) override; 283 Tick write(PacketPtr pkt) override;
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/gem5/src/mem/ruby/profiler/ |
H A D | StoreTrace.cc | 109 Tick current = curTick(); 131 Tick current = curTick();
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Completed in 24 milliseconds
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