Searched refs:GenericISA (Results 26 - 45 of 45) sorted by relevance

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/gem5/src/arch/generic/
H A Ddecode_cache.cc38 namespace GenericISA namespace
60 } // namespace GenericISA
H A Dmmapped_ipr.cc39 using namespace GenericISA;
56 GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt)
73 GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
H A Dmmapped_ipr.hh45 namespace GenericISA namespace
168 } // namespace GenericISA
H A Ddebugfaults.hh48 namespace GenericISA namespace
173 } // namespace GenericISA
H A Dtypes.hh50 namespace GenericISA namespace
/gem5/src/arch/riscv/
H A Dtypes.hh57 class PCState : public GenericISA::UPCState<MachInst>
/gem5/src/arch/alpha/
H A Ddecoder.hh91 static GenericISA::BasicDecodeCache defaultCache;
/gem5/src/arch/power/
H A Ddecoder.hh98 static GenericISA::BasicDecodeCache defaultCache;
H A Dtypes.hh81 typedef GenericISA::SimplePCState<MachInst> PCState;
/gem5/src/arch/mips/
H A Ddecoder.hh91 static GenericISA::BasicDecodeCache defaultCache;
H A Dtypes.hh43 typedef GenericISA::DelaySlotPCState<MachInst> PCState;
/gem5/src/arch/arm/
H A Ddecoder.hh84 static GenericISA::BasicDecodeCache defaultCache;
H A Ddecoder.cc55 GenericISA::BasicDecodeCache Decoder::defaultCache;
H A Dtypes.hh215 class PCState : public GenericISA::UPCState<MachInst>
219 typedef GenericISA::UPCState<MachInst> Base;
H A Dtlb.cc143 req->setPaddr(GenericISA::iprAddressPseudoInst(
/gem5/src/arch/sparc/
H A Ddecoder.hh105 static GenericISA::BasicDecodeCache defaultCache;
/gem5/src/arch/x86/
H A Dtypes.hh289 class PCState : public GenericISA::UPCState<MachInst>
292 typedef GenericISA::UPCState<MachInst> Base;
H A Dtlb.cc237 req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh488 return std::make_shared<GenericISA::M5PanicFault>(
515 return std::make_shared<GenericISA::M5PanicFault>(
H A Dlsq_unit.hh644 return std::make_shared<GenericISA::M5PanicFault>(

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