/gem5/src/mem/cache/tags/indexing_policies/ |
H A D | set_associative.hh | 91 uint32_t extractSet(const Addr addr) const; 118 std::vector<ReplaceableEntry*> getPossibleEntries(const Addr addr) const 128 Addr regenerateAddr(const Addr tag, const ReplaceableEntry* entry) const
|
/gem5/src/arch/riscv/ |
H A D | locked_mem.cc | 9 std::unordered_map<int, std::stack<Addr>> locked_addrs;
|
H A D | pagetable.hh | 50 Addr Mask; 51 Addr VPN; 57 Addr PFN0; // Physical Frame Number - Even 63 Addr PFN1; // Physical Frame Number - Odd 84 Addr _pageStart; 86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, 95 Addr pageStart() 101 updateVaddr(Addr new_vadd [all...] |
/gem5/src/base/filters/ |
H A D | block_bloom_filter.hh | 53 void set(Addr addr) override; 54 void unset(Addr addr) override; 55 int getCount(Addr addr) const override; 64 int hash(Addr addr) const;
|
/gem5/src/arch/x86/ |
H A D | vtophys.cc | 54 Addr 55 vtophys(Addr vaddr) 60 Addr 61 vtophys(ThreadContext *tc, Addr vaddr) 65 Addr addr = vaddr; 70 Addr masked_addr = vaddr & mask(logBytes); 71 Addr paddr = addr | masked_addr;
|
H A D | x86_traits.hh | 67 const Addr IntAddrPrefixMask = ULL(0xffffffff00000000); 68 const Addr IntAddrPrefixCPUID = ULL(0x100000000); 69 const Addr IntAddrPrefixMSR = ULL(0x200000000); 70 const Addr IntAddrPrefixIO = ULL(0x300000000); 72 const Addr PhysAddrPrefixIO = ULL(0x8000000000000000); 73 const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000); 74 const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000); 75 const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000); 78 const Addr PhysAddrAPICRangeSize = 1 << 12; 80 static inline Addr [all...] |
/gem5/src/cpu/testers/traffic_gen/ |
H A D | linear_gen.hh | 88 Addr start_addr, Addr end_addr, 89 Addr _blocksize, Addr cacheline_size, 91 uint8_t read_percent, Addr data_limit) 107 Addr nextAddr; 114 Addr dataManipulated;
|
H A D | dram_gen.hh | 92 Addr start_addr, Addr end_addr, 93 Addr _blocksize, Addr cacheline_size, 95 uint8_t read_percent, Addr data_limit, 120 Addr addr;
|
H A D | random_gen.hh | 84 Addr start_addr, Addr end_addr, 85 Addr _blocksize, Addr cacheline_size, 87 uint8_t read_percent, Addr data_limit) 106 Addr dataManipulated;
|
/gem5/src/cpu/ |
H A D | utils.hh | 51 inline Addr 52 addrBlockOffset(Addr addr, Addr block_size) 64 inline Addr 65 addrBlockAlign(Addr addr, Addr block_size) 79 transferNeedsBurst(Addr addr, unsigned int size, unsigned int block_size)
|
/gem5/src/dev/virtio/ |
H A D | pci.hh | 65 static const Addr OFF_DEVICE_FEATURES = 0x00; 66 static const Addr OFF_GUEST_FEATURES = 0x04; 67 static const Addr OFF_QUEUE_ADDRESS = 0x08; 68 static const Addr OFF_QUEUE_SIZE = 0x0C; 69 static const Addr OFF_QUEUE_SELECT = 0x0E; 70 static const Addr OFF_QUEUE_NOTIFY = 0x10; 71 static const Addr OFF_DEVICE_STATUS = 0x12; 72 static const Addr OFF_ISR_STATUS = 0x13; 73 static const Addr OFF_VIO_DEVICE = 0x14; 77 static const Addr BAR0_SIZE_BAS [all...] |
/gem5/src/base/loader/ |
H A D | dtb_object.hh | 67 Addr findReleaseAddr(); 69 bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, 70 Addr offset = 0, Addr addrMask = maxAddr); 71 bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, 72 Addr offset = 0, Addr addrMask = maxAddr); 73 bool loadLocalSymbols(SymbolTable *symtab, Addr base = 0, 74 Addr offset = 0, Addr addrMas [all...] |
H A D | ecoff_object.hh | 54 virtual bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, 55 Addr offset = 0, Addr addr_mask = maxAddr); 56 virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, 57 Addr offset = 0, Addr addr_mask = maxAddr); 58 virtual bool loadLocalSymbols(SymbolTable *symtab, Addr base = 0, 59 Addr offset = 0, Addr addr_mask = maxAddr);
|
H A D | aout_object.hh | 51 virtual bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, 52 Addr offset = 0, Addr addr_mask = maxAddr); 53 virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, 54 Addr offset = 0, 55 Addr addr_mask = maxAddr); 56 virtual bool loadLocalSymbols(SymbolTable *symtab, Addr base = 0, 57 Addr offset = 0, Addr addr_mask = maxAddr);
|
/gem5/src/arch/mips/ |
H A D | pagetable.hh | 50 Addr Mask; 51 Addr VPN; 57 Addr PFN0; // Physical Frame Number - Even 63 Addr PFN1; // Physical Frame Number - Odd 84 Addr _pageStart; 86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, 95 Addr pageStart() 101 updateVaddr(Addr new_vadd [all...] |
/gem5/src/sim/ |
H A D | mem_state.hh | 53 MemState(Addr brk_point, Addr stack_base, Addr max_stack_size, 54 Addr next_thread_stack_base, Addr mmap_end) 76 Addr getBrkPoint() const { return _brkPoint; } 77 Addr getStackBase() const { return _stackBase; } 78 Addr getStackSize() const { return _stackSize; } 79 Addr getMaxStackSize() const { return _maxStackSize; } 80 Addr getStackMi [all...] |
/gem5/src/dev/pci/ |
H A D | host.hh | 130 Addr pioAddr(Addr addr) const { return host.pioAddr(busAddr, addr); } 139 Addr memAddr(Addr addr) const { return host.memAddr(busAddr, addr); } 148 Addr dmaAddr(Addr addr) const { return host.dmaAddr(busAddr, addr); } 200 virtual Addr pioAddr(const PciBusAddr &bus_addr, Addr pci_addr) const = 0; 210 virtual Addr memAddr(const PciBusAddr &bus_addr, Addr pci_add [all...] |
/gem5/src/dev/arm/ |
H A D | smmu_v3_ptops.hh | 54 virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0; 55 virtual Addr index(Addr va, unsigned level) const = 0; 56 virtual Addr pageMask(pte_t pte, unsigned level) const = 0; 57 virtual Addr walkMask(unsigned level) const = 0; 67 Addr nextLevelPointer(pte_t pte, unsigned level) const override; 68 Addr index(Addr va, unsigned level) const override; 69 Addr pageMask(pte_t pte, unsigned level) const override; 70 Addr walkMas [all...] |
/gem5/src/arch/alpha/ |
H A D | isa_traits.hh | 48 const Addr PageShift = 13; 49 const Addr PageBytes = ULL(1) << PageShift; 50 const Addr PageMask = ~(PageBytes - 1); 51 const Addr PageOffset = PageBytes - 1; 58 const Addr PteShift = 3; 59 const Addr NPtePageShift = PageShift - PteShift; 60 const Addr NPtePage = ULL(1) << NPtePageShift; 61 const Addr PteMask = NPtePage - 1; 64 const Addr USegBase = ULL(0x0); 65 const Addr USegEn [all...] |
H A D | pagetable.hh | 43 static const Addr ImplMask = (ULL(1) << ImplBits) - 1; 44 static const Addr UnImplMask = ~ImplMask; 46 Addr addr; 48 VAddr(Addr a) : addr(a) {} 49 operator Addr() const { return addr; } 50 const VAddr &operator=(Addr a) { addr = a; return *this; } 52 Addr vpn() const { return (addr & ImplMask) >> PageShift; } 53 Addr page() const { return addr & PageMask; } 54 Addr offset() const { return addr & PageOffset; } 56 Addr level [all...] |
/gem5/src/mem/cache/prefetch/ |
H A D | base.hh | 94 Addr address; 96 Addr pc; 108 Addr paddress; 119 Addr getAddr() const 137 Addr getPC() const 184 Addr getPaddr() const 240 PrefetchInfo(PacketPtr pkt, Addr addr, bool miss); 248 PrefetchInfo(PrefetchInfo const &pfi, Addr addr); 287 const Addr pageBytes; 303 bool inCache(Addr add [all...] |
H A D | bop.hh | 69 std::vector<Addr> rrLeft; 70 std::vector<Addr> rrRight; 84 Addr baseAddr; 87 DelayQueueEntry(Addr x, Tick t) : baseAddr(x), processTick(t) 100 Addr bestOffset; 102 Addr phaseBestOffset; 114 unsigned int hash(Addr addr, unsigned int way) const; 120 void insertIntoRR(Addr addr, unsigned int way); 126 void insertIntoDelayQueue(Addr addr); 135 Addr ta [all...] |
/gem5/src/arch/x86/regs/ |
H A D | msr.hh | 42 typedef std::unordered_map<Addr, MiscRegIndex> MsrMap; 64 bool msrAddrToIndex(MiscRegIndex ®Num, Addr addr);
|
/gem5/src/arch/sparc/ |
H A D | isa_traits.hh | 47 const Addr PageShift = 13; 48 const Addr PageBytes = ULL(1) << PageShift;
|
/gem5/src/mem/ruby/structures/ |
H A D | PerfectCacheMemory.hh | 59 bool isTagPresent(Addr address) const; 64 bool cacheAvail(Addr address) const; 67 void allocate(Addr address); 69 void deallocate(Addr address); 72 Addr cacheProbe(Addr newAddress) const; 75 ENTRY* lookup(Addr address); 76 const ENTRY* lookup(Addr address) const; 79 AccessPermission getPermission(Addr address) const; 80 void changePermission(Addr addres [all...] |