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| /gem5/src/arch/x86/ | ||
| H A D | utility.cc | 9751:e039a48eeb99 Tue Jun 11 03:24:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> x86: Fix bug when copying TSC on CPU handover The TSC value stored in MISCREG_TSC is actually just an offset from the current CPU cycle to the actual TSC value. Writes with side-effects to the TSC subtract the current cycle count before storing the new value, while reads add the current cycle count. When switching CPUs, the current value is copied without side-effects. This works as long as the source and the destination CPUs have the same clock frequencies. The TSC will jump, sometimes backwards, if they have different clock frequencies. Most OSes assume the TSC to be monotonic and break when this happens. This changeset makes sure that the TSC is copied with side-effects to ensure that the offset is updated to match the new CPU. |
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