Searched hist:9628 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/slicc/ast/
H A DIfStatementAST.py9628:195d92059654 Tue Apr 09 17:12:00 EDT 2013 Jason Power <powerjg@cs.wisc.edu> Ruby: Fix typo in Slicc if-statement AST error

The error in the SLICC code was hidden by the python error in SLICC parser
before this patch
/gem5/src/sim/
H A Dsyscall_emul.hh13649:d1bb2eb7d0f6 Mon Apr 02 16:22:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> sim: handle the case when there're not enough HW thread contexts

In SE mode, since there's no OS scheduler, the number of active SW
threads is limited by the number of HW thread contexts. Previously, if
there is no spare HW thread context, the simulator just fails and stops.
Instead, this patch returns EAGAIN error code from a clone syscall if
there's no available HW thread context. Then it's up to the simulated
program to handle the error.

Linux man page reference:
http://man7.org/linux/man-pages/man2/clone.2.html
http://man7.org/linux/man-pages/man2/fork.2.html

Change-Id: Ib4e092433e49de4dde376c8cb81f7d3f7851cbc0
Reviewed-on: https://gem5-review.googlesource.com/c/9628
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

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