Searched hist:8140 (Results 1 - 9 of 9) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | intregs.hh | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| /gem5/src/arch/arm/isa/templates/ | ||
| H A D | macromem.isa | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| H A D | mem.isa | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | mem.isa | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| H A D | ldr.isa | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| H A D | macromem.isa | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| /gem5/src/arch/arm/insts/ | ||
| H A D | macromem.hh | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| H A D | macromem.cc | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
| H A D | mem.hh | 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. |
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