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| H A D | lsq_unit_impl.hh | 8133:9f704aa10eb4 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Fix unaligned stores when cache blocked Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever. |
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