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H A Dtable_walker.hh7728:cf9db1c47a77 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Don't return the result of a table walk the same cycle it's completed.

The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock cycle
when the translation completes.

Also prevent multiple outstanding table walks from occuring at once.
H A Dtable_walker.cc7728:cf9db1c47a77 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Don't return the result of a table walk the same cycle it's completed.

The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock cycle
when the translation completes.

Also prevent multiple outstanding table walks from occuring at once.

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