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| /gem5/src/cpu/simple/ | ||
| H A D | timing.cc | 7516:cfbbc9178e7a Thu Aug 12 20:16:00 EDT 2010 Joel Hestness <hestness@cs.utexas.edu> TimingSimpleCPU: fix NO_ACCESS memory op handling When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse |
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