Searched hist:6301 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/ | ||
| H A D | loop.py | 12361:ed9f9d629a7e Mon Dec 04 21:30:00 EST 2017 Gabe Black <gabeblack@google.com> x86: LOOP's operand size defaults to 64 bits in 64 bit mode. The microcode for those instructions needs a directive which overrides that setting in the instructions emulation environment. Reported-by: Matt Sinclair <mattdsinclair@gmail.com> Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967 Reviewed-on: https://gem5-review.googlesource.com/6301 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/arm/insts/ | ||
| H A D | mem.hh | 6301:719e56579870 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add an AddrMode3 format for memory instructions that use address mode 3. |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | mem.isa | 6301:719e56579870 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add an AddrMode3 format for memory instructions that use address mode 3. |
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