Searched hist:6181 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/alpha/isa/
H A Dpal.isa6181:19fedb1e5ded Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
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H A Dmem.isa6181:19fedb1e5ded Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
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/gem5/src/arch/riscv/isa/formats/
H A Dmem.isa12327:38a7e269ae2a Wed Nov 29 00:12:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove spaces around ea_code

This patch makes mem.isa conform to style guidelines better by removing
spaces around the "ea_code" argument default value assignment of the
Load format.

Change-Id: I1c62b99de3617a3734b128b00fb421773e021317
Reviewed-on: https://gem5-review.googlesource.com/6181
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
/gem5/src/cpu/
H A DSConscript6181:19fedb1e5ded Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
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