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| /gem5/configs/common/ | ||
| H A D | MemConfig.py | 10677:5935ab1ddd7a Tue Feb 03 14:25:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> config: Add XOR hashing to the DRAM channel interleaving This patch uses the recently added XOR hashing capabilities for the DRAM channel interleaving. This avoids channel biasing due to strided access patterns. |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | regop.isa | 5935:df55109af564 Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the TSS type check actually return a fault if it fails. |
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