Searched hist:5862 (Results 1 - 2 of 2) sorted by relevance
/gem5/src/arch/arm/insts/ | ||
H A D | misc.cc | 12281:90315832cb81 Wed Nov 15 10:27:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MCR/MRC disassemble This patch is fixing the Aarch32 MCR/MRC disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the coprocessor register name Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5862 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/ | ||
H A D | SConscript | 5862:50fb2cb40609 Mon Feb 09 23:10:00 EST 2009 Nathan Binkert <nate@binkert.org> scons: Don't build the intermediate static library unless explicitly requested. This means that similar to libm5_fast.so, you need to explicitly build build/ALPHA_SE/libm5_fast.a if you want it. |
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