Searched hist:5861 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/arch/arm/insts/ | ||
| H A D | misc64.hh | 12280:a44a2326a02b Fri Nov 10 10:35:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MSR/MRS disassemble This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | misc64.cc | 12280:a44a2326a02b Fri Nov 10 10:35:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MSR/MRS disassemble This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/templates/ | ||
| H A D | misc64.isa | 12280:a44a2326a02b Fri Nov 10 10:35:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MSR/MRS disassemble This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | data64.isa | 12280:a44a2326a02b Fri Nov 10 10:35:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MSR/MRS disassemble This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | aarch64.isa | 12280:a44a2326a02b Fri Nov 10 10:35:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MSR/MRS disassemble This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | regop.isa | 5861:8c1aa74572e4 Fri Feb 06 23:55:00 EST 2009 Nathan Binkert <nate@binkert.org> Quell g++ 4.3 warning about operator ambiguity |
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