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/gem5/src/arch/sparc/isa/formats/
H A Dbasic.isa4011:e6899d7ca5b1 Tue Feb 06 15:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
/gem5/src/arch/sparc/isa/formats/mem/
H A Dblockmem.isa3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
/gem5/src/arch/arm/isa/insts/
H A Dldr.isa7336:52dc042584d6 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the VLDR instruction.
/gem5/src/arch/arm/
H A Dnativetrace.cc6398:7a94cba72e02 Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make native trace only print when registers are changing value.
When registers have incorrect values but aren't actively changing, it's likely
they're not being modified at all. The fact that they're still wrong isn't
very important.
H A DSConscript9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change.
H A Disa.hh12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
6401:4e9d4c206930 Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Initialize the CPSR so that we're in user mode.
/gem5/src/arch/mips/
H A Dutility.hh4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
H A Dprocess.hh2909:4f5e7d6fab54 Fri Jul 14 04:52:00 EDT 2006 Korey Sewell <ksewell@umich.edu> MIPS specific fixes ... the main thing is that SMT threads get their own stack space instead of all stacks start to space

src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc11363:f3f72c0ab03e Fri Nov 27 09:52:00 EST 2015 Andreas Sandberg <andreas@sandberg.pp.se> kvm: Shutdown KVM and disconnect performance counters on fork

We can't/shouldn't use KVM after a fork since the child and parent
probably point to the same VM. Knowing the exact effects of this is
hard, but they are likely to be messy. We also disconnect the
performance counters attached to the guest. This works around what
seems to be a kernel bug where spurious SIGIOs get delivered to the
forked child process.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Fatal if entering KVM in child process ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dbase.cc11399:3f805b5c48ae Wed Mar 30 05:52:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> kvm: Add an option to force context sync on kvm entry/exit

This changeset adds an option to force the kvm-based CPUs to always
synchronize the gem5 thread context representation on entry/exit into
the kernel. This is very useful for debugging. Unfortunately, it is
also the only way to get reliable register contents when using remote
gdb functionality. The long-term solution for the latter would be to
implement a kvm-specific thread context.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Alexandru Dutu <alexandru.dutu@amd.com>
11363:f3f72c0ab03e Fri Nov 27 09:52:00 EST 2015 Andreas Sandberg <andreas@sandberg.pp.se> kvm: Shutdown KVM and disconnect performance counters on fork

We can't/shouldn't use KVM after a fork since the child and parent
probably point to the same VM. Knowing the exact effects of this is
hard, but they are likely to be messy. We also disconnect the
performance counters attached to the guest. This works around what
seems to be a kernel bug where spurious SIGIOs get delivered to the
forked child process.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Fatal if entering KVM in child process ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/cache/prefetch/
H A Dstride.cc13427:72a3afac3e78 Sun Nov 11 09:52:00 EST 2018 Daniel <odanrc@yahoo.com.br> mem-cache: Make StridePrefetcher use Replacement Policies

Previously StridePrefetcher was only able to use random
replacement policy. This change allows all replacement
policies to be applied to the pc table.

Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14360
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/sim/
H A Dsim_events.hh11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default

Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
H A Dclocked_object.hh11424:e07fd01651f3 Tue Apr 05 11:52:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> power: Add support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Finally, the thermal model is updated to use the power usage as input.
H A DSConscript11424:e07fd01651f3 Tue Apr 05 11:52:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> power: Add support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Finally, the thermal model is updated to use the power usage as input.
9827:f47274776aa0 Mon Aug 19 03:52:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> power: Add voltage domains to the clock domains

This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.

A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.

The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.

The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
/gem5/src/systemc/core/
H A Dkernel.cc13077:0037323cb4dd Wed Aug 22 20:52:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: If sc_main returns, don't do any more systemc stuff.

When sc_main returns, clear out any pending work in the scheduler and
also block the systemc kernel from doing actions which correspond with
the start of simulation.

It's most likely that work like oustanding timeouts might survive past
the end of sc_main, especially if it never officially called sc_stop.
It's also possible for sc_main to return and never actually call
sc_start. In that case, the kernel should not call callbacks of the
various objects (which may no longer even exist), or go through the
initialization phase.

If sc_main is never called at all, then the kernel's actions aren't
gated.

Change-Id: I49bf094be3283a92d846d2f3da224950bd893a5c
Reviewed-on: https://gem5-review.googlesource.com/12249
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/unittest/
H A DSConscript12379:52b13ae47c42 Sun Dec 03 04:59:00 EST 2017 Gabe Black <gabeblack@google.com> tests: Move the trietest unit test into base.

This puts it alongside trie.hh, the header file it tests.

Change-Id: Id8ca0c1d68bdc01807c5ba4b51c0142b1221385d
Reviewed-on: https://gem5-review.googlesource.com/6281
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
/gem5/util/stats/
H A Dstats.py1604:c986abdfc71f Thu Mar 24 15:52:00 EST 2005 Ron Dreslinski <rdreslin@umich.edu> Update so that statistics can be plotted correctly

util/stats/stats.py:
Changed some stuff for graphing purposes:
full_cpu is now full0
frequencies are now s,m,f,q not s,6,8,q
L2 is now l2
etherdev is now etherdev0

May want to consider fact that NAT box should be the sum of etherdev0 and etherdev1 (not in script yet)
/gem5/util/
H A Dstyle.py6825:104115ebc206 Fri Aug 21 16:52:00 EDT 2009 pdudnik@gmail.com [mq]: first_patch
/gem5/configs/common/
H A DMemConfig.py9836:4411b4e0c03a Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Command line support for multi-channel memory

This patch adds support for specifying multi-channel memory
configurations on the command line, e.g. 'se/fs.py
--mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it
enhances the functionality of MemConfig and moves the existing
makeMultiChannel class method from SimpleDRAM to the support scripts.

The se/fs.py example scripts are updated to make use of the new
feature.
/gem5/src/arch/alpha/
H A Dsystem.cc8885:52bbd95b31ed Fri Mar 09 09:59:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> System: Move code in initState() back into constructor whenever possible.

The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
/gem5/src/mem/
H A Dpacket_queue.cc13565:fe1169a7502d Tue Dec 04 10:52:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Allow inserts in the begining of a packet queue

A packet queue keeps track of packets that are scheduled to be sent at
a specified time. Packets are sorted such that the packet with the
earliest scheduled time is at the front of the list (unless there are
other ordering requirements). Previouly, the implemented algorithm
didn't allow packets to be placed at the front of the queue resulting
in uneccessary delays. This change fixes the implementation of
schedSendTiming.

Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15556
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dtport.hh8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split

This patch splits the two cache ports into a master (memory-side) and
slave (cpu-side) subclass of port with slightly different
functionality. For example, it is only the CPU-side port that blocks
incoming requests, and only the memory-side port that schedules send
events outside of what the transmit list dictates.

This patch simplifies the two classes by relying further on
SimpleTimingPort and also generalises the latter to better accommodate
the changes (introducing trySendTiming and scheduleSend). The
memory-side cache port overrides sendDeferredPacket to be able to not
only send responses from the transmit list, but also send requests
based on the MSHRs.

A follow on patch further simplifies the SimpleTimingPort and the
cache ports.
/gem5/src/arch/riscv/
H A Dregisters.hh11911:fecd8de0ec8e Wed Mar 01 15:52:00 EST 2017 Brandon Potter <Brandon.Potter@amd.com> syscall-emul: Rewrite system call exit code

The changeset does a major refactor on the exit, exit_group, and
futex system calls regarding exit functionality.

A FutexMap class and related structures are added into a new
file. This increases code clarity by encapsulating the futex
operations and the futex state into an object.

Several exit conditions were added to allow the simulator to end
processes under certain conditions. Also, the simulation only
exits now when all processes have finished executing.

Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e
Reviewed-on: https://gem5-review.googlesource.com/2269
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/dev/arm/
H A DGic.py14179:9e01b57898e0 Mon Aug 19 08:52:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm,system-arm: missing GICv3 ranges property

This patch adds the device tree "ranges" property to GICv3 for
the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB
auto generation.
This allows the GICv3 ITS to be specified in the device tree.

Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/base/
H A Dstatistics.hh9865:cc5797147e1c Mon Sep 09 19:52:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> stats: add operator= for DataWrapVec class

gcc/g++ 4.4.7 complained about the operator= being undefined.
This changeset adds the operator.
4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and
expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.

Completed in 251 milliseconds

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