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/gem5/ext/fputils/
H A DMakefile.am10480:5d4ebc92d32e Thu Oct 16 05:49:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> ext: Update fputils to rev 6a47fd8358

This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
/gem5/src/arch/mips/bare_iron/
H A Dsystem.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
H A Dsystem.cc5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
/gem5/src/arch/x86/regs/
H A Dmsr.cc9875:5cfad3486991 Wed Sep 18 05:28:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> x86: Expose the raw hash map of MSRs

This patch allows the KVM CPU module to initialize it's MSRs by
enumerating the MSRs in the gem5 x86 implementation.
/gem5/util/statetrace/
H A DSConstruct8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/util/statetrace/arch/sparc/
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/util/statetrace/arch/arm/
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/ext/fputils/include/fputils/
H A Dfptypes.h10480:5d4ebc92d32e Thu Oct 16 05:49:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> ext: Update fputils to rev 6a47fd8358

This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
/gem5/build_opts/
H A DRISCV11727:055ae402fbd0 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 5/5] Added missing support for timing CPU models

Last of five patches adding RISC-V to GEM5. This patch adds support for
timing, minor, and detailed CPU models that was missing in the last four,
which basically consists of handling timing-mode memory accesses and
telling the minor and detailed models what a no-op instruction should
be (addi zero, zero, 0).

Patches 1-4 introduced RISC-V and implemented the base instruction set,
RV64I, and added the multiply, floating point, and atomic memory
extensions, RV64MAFD.

[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
[Fixed some style errors in locked_mem.hh.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
11727:055ae402fbd0 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 5/5] Added missing support for timing CPU models

Last of five patches adding RISC-V to GEM5. This patch adds support for
timing, minor, and detailed CPU models that was missing in the last four,
which basically consists of handling timing-mode memory accesses and
telling the minor and detailed models what a no-op instruction should
be (addi zero, zero, 0).

Patches 1-4 introduced RISC-V and implemented the base instruction set,
RV64I, and added the multiply, floating point, and atomic memory
extensions, RV64MAFD.

[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
[Fixed some style errors in locked_mem.hh.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/arm/freebsd/
H A Dprocess.hh11851:824055fe6b30 Wed Nov 09 15:27:00 EST 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
/gem5/src/kern/freebsd/
H A Dfreebsd.hh11851:824055fe6b30 Wed Nov 09 15:27:00 EST 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
/gem5/tests/quick/se/10.mcf/
H A Dtest.py11851:824055fe6b30 Wed Nov 09 15:27:00 EST 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
/gem5/tests/quick/se/30.eon/
H A Dtest.py11851:824055fe6b30 Wed Nov 09 15:27:00 EST 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
/gem5/src/arch/generic/
H A Dvec_pred_reg.hh13610:5d5404ac6288 Tue Oct 16 11:04:00 EDT 2018 Giacomo Gabrielli <giacomo.gabrielli@arm.com> arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/mem/cache/prefetch/
H A Ddelta_correlating_prediction_tables.cc13667:e3ae3619b9ab Tue Feb 05 17:31:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Delta Correlating Prediction Tables Prefetcher

Reference:
Multi-level hardware prefetching using low complexity delta correlating
prediction tables with partial matching.
Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
In Proceedings of the 5th international conference on High Performance
Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Ddelta_correlating_prediction_tables.hh13667:e3ae3619b9ab Tue Feb 05 17:31:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Delta Correlating Prediction Tables Prefetcher

Reference:
Multi-level hardware prefetching using low complexity delta correlating
prediction tables with partial matching.
Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
In Proceedings of the 5th international conference on High Performance
Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron_64KB.cc14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dmultiperspective_perceptron_64KB.hh14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dmultiperspective_perceptron_8KB.cc14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dmultiperspective_perceptron_8KB.hh14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dmultiperspective_perceptron_tage.cc14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dmultiperspective_perceptron_tage.hh14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dmultiperspective_perceptron_tage_64KB.cc14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dmultiperspective_perceptron_tage_64KB.hh14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>

Completed in 30 milliseconds

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