Searched hist:5 (Results 176 - 200 of 1055) sorted by relevance
| /gem5/src/arch/riscv/isa/formats/ | ||
| H A D | formats.isa | 11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/riscv/isa/ | ||
| H A D | operands.isa | 11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | bitfields.isa | 13931:31e62b71cca6 Thu Apr 04 16:20:00 EDT 2019 Avishai Tvila <avishai.tvila@gmail.com> arch-riscv,isa: Fix for compressed jump (c_j) imm c_j(al) has a special format, called CJ. The jump offset format is instbits[12:2] --> offset[11|4|9:8|10|6|7|3:1|5] Currently in decoder.isa, c_j format is JOp, the imm and branchTarget are incorrect In the execute section (decoder.isa:228), the imm fields is ignored and the offset is calculated correctlly. As a result, we get decoder flush for each c_j instance I've added CJOp format in compressed.isa, and use it in execute section. In addition, c_j is mappped to jal zero, cj_imm, and actually is neither indirect control nor a function call I fixed the flags accordently. I'll fix all IsRet, IsCall and IsIndirectControl flags for rest of (c_)jal(r) in my next commit. I ran coremark -O0 before my fix and I got 37.7% branch miss-rate, after the fix the branch miss-rate is <13% Change-Id: I608d5894a78a1ebefe36f21e21aaea68b42bccfc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17808 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> 11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> 11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and at |