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/gem5/src/mem/
H A Dtport.hh4871:02c0ad6e09ee Sat Jun 30 16:34:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix up a few statistics problems.
Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence

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