Searched hist:3880 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/cpu/ | ||
| H A D | exetrace.cc | 3880:06fc2b8ca95f Wed Dec 27 14:35:00 EST 2006 Ali Saidi <saidi@eecs.umich.edu> Compare legion and m5 tlbs for differences Only print faults instructions that aren't traps or faulting loads src/cpu/exetrace.cc: Compare the legion and m5 tlbs and printout any differences Only show differences if the instruction isn't a trap and isn't a memory operation that changes the trap level (a fault) src/cpu/m5legion_interface.h: update the m5<->legion interface to add tlb data |
| /gem5/src/mem/cache/ | ||
| H A D | base.hh | 12091:f2d1af96ad2d Tue Jun 13 06:28:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> mem-cache: Add missing overrides to BaseCache Change-Id: I6a3a57e3067c247bd6ce6f01ac9459883f4aae2c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3880 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
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