Searched hist:3481 (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/isa/insts/
H A Dneon64.isa12038:619bc4100aa8 Tue Apr 25 13:35:00 EDT 2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> arch-arm: Fix some poorly done type max and min in NEON

The ISA code for ARM calculates min and max elements for types using
bit manipulation. That triggers some warnings, treated as errors, as
the compiler can tell that there is an overflow and the sign
flips. Fixed using standard lib definitions instead.

Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dneon.isa12038:619bc4100aa8 Tue Apr 25 13:35:00 EDT 2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> arch-arm: Fix some poorly done type max and min in NEON

The ISA code for ARM calculates min and max elements for types using
bit manipulation. That triggers some warnings, treated as errors, as
the compiler can tell that there is an overflow and the sign
flips. Fixed using standard lib definitions instead.

Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/configs/common/
H A DSimulation.py3481:14362d3b0756 Wed Nov 01 19:25:00 EST 2006 Lisa Hsu <hsul@eecs.umich.edu> factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.

configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.
/gem5/configs/example/
H A Dfs.py3481:14362d3b0756 Wed Nov 01 19:25:00 EST 2006 Lisa Hsu <hsul@eecs.umich.edu> factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.

configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.
H A Dse.py3481:14362d3b0756 Wed Nov 01 19:25:00 EST 2006 Lisa Hsu <hsul@eecs.umich.edu> factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.

configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.

Completed in 91 milliseconds