Searched hist:3137 (Results 1 - 5 of 5) sorted by relevance

/gem5/src/mem/ruby/structures/
H A DRubyCache.py11052:3137d34acf29 Fri Aug 21 07:03:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> ruby: Move Rubys cache class from Cache.py to RubyCache.py

This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.
H A DSConscript11052:3137d34acf29 Fri Aug 21 07:03:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> ruby: Move Rubys cache class from Cache.py to RubyCache.py

This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.
/gem5/configs/ruby/
H A DMI_example.py11052:3137d34acf29 Fri Aug 21 07:03:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> ruby: Move Rubys cache class from Cache.py to RubyCache.py

This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.
/gem5/src/mem/ruby/system/
H A DSequencer.hh6886:3137c3d41107 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Converted the sequencer deadlock event to m5 eventq
H A DSequencer.cc6886:3137c3d41107 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Converted the sequencer deadlock event to m5 eventq

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