Searched hist:2015 (Results 726 - 750 of 1505) sorted by relevance

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/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/
H A Dstats.txt11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/
H A Dstats.txt11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
/gem5/src/mem/ruby/slicc_interface/
H A DMessage.hh10987:a618349a7953 Sat Aug 01 00:59:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> ruby: removed invalid assert in message comparitor

It is perfectly valid to compare the same message and the greater than
operator should work correctly.
10895:287285860dd6 Sat Jul 04 11:43:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.
10893:f567e80c0714 Sat Jul 04 11:43:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove message buffer node

This structure's only purpose was to provide a comparison function for
ordering messages in the MessageBuffer. The comparison function is now
being moved to the Message class itself. So we no longer require this
structure.
10876:7544f29b7dfc Thu Jun 25 12:58:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: message: remove a data member added by mistake

I (Nilay) had mistakenly added a data member to the Message class in revision c1694b4032a6.
The data member is being removed.
10808:c1694b4032a6 Wed Apr 29 23:35:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: set: replace long by unsigned long
UBSan complains about negative value being shifted
H A DAbstractController.cc11309:9be8a40026df Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: split CPU and GPU latency stats
11142:c5ac64b4b020 Tue Sep 29 10:28:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Fix memory leak in AbstractController

Recent changes to memory access queuing allocate requests for packets sent to
memory controllers, but did not free the requests. Delete them to avoid leaks.
11118:75c1e564a725 Fri Sep 18 14:27:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.
11111:6da33e720481 Wed Sep 16 12:59:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
11108:6342ddf6d733 Wed Sep 16 00:03:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.
11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
11024:bc179fa0b91b Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: rename variables Addr to addr

Avoid clash between type Addr and variable name Addr.
11021:e8a6637afa4c Fri Aug 14 01:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.
10986:4fbe4b0adb4d Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> ruby: improved stall and wait debugging

Added dprintfs and asserts for identifying stall and wait bugs.
10977:9b3b9be42dd9 Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: Fix for stallAndWait bug

It was previously possible for a stalled message to be reordered after an
incomming message. This patch ensures that any stalled message stays in its
original request order.
H A DRubyRequest.cc11118:75c1e564a725 Fri Sep 18 14:27:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.
11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
/gem5/src/mem/ruby/network/simple/
H A DThrottle.cc11111:6da33e720481 Wed Sep 16 12:59:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
11108:6342ddf6d733 Wed Sep 16 00:03:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.
11092:a51ef09e3a78 Sat Sep 12 17:16:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:

a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.

b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.
11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040
11037:91d6a2d95cf8 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: simple network: store Switch* in PerfectSwitch and Throttle
11021:e8a6637afa4c Fri Aug 14 01:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.
10919:80069a602c83 Fri Jul 10 17:05:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.
10918:dd3ab1f109ad Fri Jul 10 17:05:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> ruby: replace g_ruby_start with per-RubySystem m_start_cycle

This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.

This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.
10895:287285860dd6 Sat Jul 04 11:43:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.
H A DThrottle.hh11108:6342ddf6d733 Wed Sep 16 00:03:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.
11092:a51ef09e3a78 Sat Sep 12 17:16:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:

a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.

b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.
11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040
11037:91d6a2d95cf8 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: simple network: store Switch* in PerfectSwitch and Throttle
10920:58fbfddff18d Fri Jul 10 17:05:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> ruby: replace global g_abs_controls with per-RubySystem var

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.

Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.
10918:dd3ab1f109ad Fri Jul 10 17:05:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> ruby: replace g_ruby_start with per-RubySystem m_start_cycle

This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.

This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.
H A DSimpleNetwork.hh11124:5d38dc2f7d66 Thu Sep 24 09:41:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.
11113:5a2e1b1b5c43 Wed Sep 16 13:10:00 EDT 2015 Joe Gross <joe.gross@amd.com> ruby: fix message buffer init order

The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.

This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.
11064:386a5200e298 Sun Aug 30 01:24:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: drop member m_in_use

This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.

Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.
11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040
11047:dcf729f0bbfa Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.
11021:e8a6637afa4c Fri Aug 14 01:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.
/gem5/src/dev/
H A DSConscript11264:dc389d2d2f79 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move storage devices to src/dev/storage/

Move the IDE controller and the disk implementations to
src/dev/storage.
11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
11262:3aeb879a66e6 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move i2c functionality to src/dev/i2c/
11261:2050602b55f7 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move the CopyEngine class to src/dev/pci
11260:bedcc64f6145 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move existing PCI device functionality to src/dev/pci

Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.
11244:a2af58a06c4e Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Rewrite PCI host functionality

The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.

* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.

* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
11012:f2ca575d27fd Fri Aug 07 04:59:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Implement a simple display timing generator

Timing generator for a pixel-based display. The timing generator is
intended for display processors driving a standard rasterized
display. The simplest possible display processor needs to derive from
this class and override the nextPixel() method to feed the display
with pixel data.

Pixels are ordered relative to the top left corner of the
display. Scan lines appear in the following order:

* Vertical Sync (starting at line 0)
* Vertical back porch
* Visible lines
* Vertical front porch

Pixel order within a scan line:

* Horizontal Sync
* Horizontal Back Porch
* Visible pixels
* Horizontal Front Porch

All events in the timing generator are automatically suspended on a
drain() request and restarted on drainResume(). This is conceptually
equivalent to clock gating when the pixel clock while the system is
draining. By gating the pixel clock, we prevent display controllers
from disturbing a memory system that is about to drain.
10923:5fe05690d03d Wed Jul 15 20:53:00 EDT 2015 Gabor Dozsa <gabor.dozsa@arm.com> dev: add support for multi gem5 runs

Multi gem5 is an extension to gem5 to enable parallel simulation of a
distributed system (e.g. simulation of a pool of machines
connected by Ethernet links). A multi gem5 run consists of seperate gem5
processes running in parallel (potentially on different hosts/slots on
a cluster). Each gem5 process executes the simulation of a component of the
simulated distributed system (e.g. a multi-core board with an Ethernet NIC).

The patch implements the "distributed" Ethernet link device
(dev/src/multi_etherlink.[hh.cc]). This device will send/receive
(simulated) Ethernet packets to/from peer gem5 processes. The interface
to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and
in tcp_iface.hh.

There is also a central message server process (util/multi/tcp_server.[hh,cc])
which acts like an Ethernet switch and transfers messages among the gem5 peers.

A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh
wrapper script.

Checkpoints are supported by multi-gem5. The checkpoint must be
initiated by a single gem5 process. E.g., the gem5 process with rank 0
can take a checkpoint from the bootscript just before it invokes
'mpirun' to launch an MPI test. The message server process will notify
all the other peer gem5 processes and make them take a checkpoint, too
(after completing a global synchronisation to ensure that there are no
inflight messages among gem5).
10800:c0957cf9f606 Thu Apr 23 13:37:00 EDT 2015 Peter Enns <Peter.Enns@arm.com> dev: Add support for i2c devices

This patch adds an I2C bus and base device. I2C is used to connect a
variety of sensors, and this patch serves as a starting point to
enable a range of I2C devices.
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/
H A Dstats.txt11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/
H A Dstats.txt11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/
H A Dstats.txt11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/
H A Dstats.txt11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/
H A Dstats.txt11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/src/dev/arm/
H A Dhdlcd.cc11359:b0b976a1ceda Fri Nov 27 09:41:00 EST 2015 Andreas Sandberg <andreas@sandberg.pp.se> base: Add support for changing output directories

This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.

This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
11091:62e1504b9c64 Fri Sep 11 10:56:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add an underrun statistic to the HDLCD controller

Add a stat that counts buffer underruns in the HDLCD controller. The
stat counts at most one underrun per frame since the controller aborts
the current frame if it underruns.
11090:f37a6b82f98f Fri Sep 11 10:55:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Rewrite the HDLCD controller

Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:

* Broken/missing interrupt support (VSync, underrun, DMA end)
* Fragile resolution changes (changing resolutions used
to cause assertion errors).
* Support for resolutions with a width that isn't divisible by 32.
* The pixel clock can now be set dynamically.

This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
10840:48039363f67a Sat May 23 08:37:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> arm: Workaround incorrect HDLCD register order in kernel

Some versions of the kernel incorrectly swap the red and blue color
select registers. This changeset adds a workaround for that by
swapping them when instantiating a PixelConverter.
10839:10cac0f0f419 Sat May 23 08:37:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> base: Redesign internal frame buffer handling

Currently, frame buffer handling in gem5 is quite ad hoc. In practice,
we pass around naked pointers to raw pixel data and expect consumers
to convert frame buffers using the (broken) VideoConverter.

This changeset completely redesigns the way we handle frame buffers
internally. In summary, it fixes several color conversion bugs, adds
support for more color formats (e.g., big endian), and makes the code
base easier to follow.

In the new world, gem5 always represents pixel data using the Pixel
struct when pixels need to be passed between different classes (e.g.,
a display controller and the VNC server). Producers of entire frames
(e.g., display controllers) should use the FrameBuffer class to
represent a frame.

Frame producers are expected to create one instance of the FrameBuffer
class in their constructors and register it with its consumers
once. Consumers are expected to check the dimensions of the frame
buffer when they consume it.

Conversion between the external representation and the internal
representation is supported for all common "true color" RGB formats of
up to 32-bit color depth. The external pixel representation is
expected to be between 1 and 4 bytes in either big endian or little
endian. Color channels are assumed to be contiguous ranges of bits
within each pixel word. The external pixel value is scaled to an 8-bit
internal representation using a floating multiplication to map it to
the entire 8-bit range.
/gem5/src/mem/
H A Dsimple_mem.hh11193:564e2e7e86f4 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Use the packet delays and do not just zero them out

This patch updates the I/O devices, bridge and simple memory to take
the packet header and payload delay into account in their latency
calculations. In all cases we add the header delay, i.e. the
accumulated pipeline delay of any crossbars, and the payload delay
needed for deserialisation of any payload.

Due to the additional unknown latency contribution, the packet queue
of the simple memory is changed to use insertion sorting based on the
time stamp. Moreover, since the memory hands out exclusive (non
shared) responses, we also need to ensure ordering for reads to the
same address.
11190:0964165d1857 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Unify delayed packet deletion

This patch unifies how we deal with delayed packet deletion, where the
receiving slave is responsible for deleting the packet, but the
sending agent (e.g. a cache) is still relying on the pointer until the
call to sendTimingReq completes. Previously we used a mix of a
deletion vector and a construct using unique_ptr. With this patch we
ensure all slaves use the latter approach.
11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10913:38dbdeea7f1f Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor and simplify the drain API

The drain() call currently passes around a DrainManager pointer, which
is now completely pointless since there is only ever one global
DrainManager in the system. It also contains vestiges from the time
when SimObjects had to keep track of their child objects that needed
draining.

This changeset moves all of the DrainState handling to the Drainable
base class and changes the drain() and drainResume() calls to reflect
this. Particularly, the drain() call has been updated to take no
parameters (the DrainManager argument isn't needed) and return a
DrainState instead of an unsigned integer (there is no point returning
anything other than 0 or 1 any more). Drainable objects should return
either DrainState::Draining (equivalent to returning 1 in the old
system) if they need more time to drain or DrainState::Drained
(equivalent to returning 0 in the old system) if they are already in a
consistent state. Returning DrainState::Running is considered an
error.

Drain done signalling is now done through the signalDrainDone() method
in the Drainable class instead of using the DrainManager directly. The
new call checks if the state of the object is DrainState::Draining
before notifying the drain manager. This means that it is safe to call
signalDrainDone() without first checking if the simulator has
requested draining. The intention here is to reduce the code needed to
implement draining in simple objects.
10713:eddb533708cb Mon Mar 02 04:00:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Split port retry for all different packet classes

This patch fixes a long-standing isue with the port flow
control. Before this patch the retry mechanism was shared between all
different packet classes. As a result, a snoop response could get
stuck behind a request waiting for a retry, even if the send/recv
functions were split. This caused message-dependent deadlocks in
stress-test scenarios.

The patch splits the retry into one per packet (message) class. Thus,
sendTimingReq has a corresponding recvReqRetry, sendTimingResp has
recvRespRetry etc. Most of the changes to the code involve simply
clarifying what type of request a specific object was accepting.

The biggest change in functionality is in the cache downstream packet
queue, facing the memory. This queue was shared by requests and snoop
responses, and it is now split into two queues, each with their own
flow control, but the same physical MasterPort. These changes fixes
the previously seen deadlocks.
/gem5/src/base/
H A Dpollevent.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
H A Dcp_annotate.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
/gem5/src/cpu/kvm/
H A DSConscript10859:0ba6f47025d1 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm, dev: Add an in-kernel GIC implementation

This changeset adds a GIC implementation that uses the kernel's
built-in support for simulating the interrupt controller. Since there
is currently no support for state transfer between gem5 and the
kernel, the device model does not support serialization and CPU
switching (which would require switching to a gem5-simulated GIC).
10857:d2d5212578db Mon Jun 01 14:43:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Move ARM-specific files to arch/arm/kvm/

This changeset moves the ARM-specific KVM CPU implementation to
arch/arm/kvm/. This change is expected to keep the source tree
somewhat cleaner as we start adding support for ARMv8 and KVM
in-kernel interrupt controller simulation.
/gem5/src/mem/ruby/network/
H A DSConscript11021:e8a6637afa4c Fri Aug 14 01:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.
10893:f567e80c0714 Sat Jul 04 11:43:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove message buffer node

This structure's only purpose was to provide a comparison function for
ordering messages in the MessageBuffer. The comparison function is now
being moved to the Message class itself. So we no longer require this
structure.
/gem5/src/sim/
H A Ddebug.hh11164:b6c6c55b59ac Fri Oct 09 15:27:00 EDT 2015 Dylan Johnson <Dylan.Johnson@ARM.com> sim: Add relative break scheduling

Add schedRelBreak() function, executable within a debugger, that sets a
breakpoint by relative rather than absolute tick.
11157:bc07f3764129 Wed Sep 02 14:34:00 EDT 2015 Dylan Johnson <Dylan.Johnson@ARM.com> sim: Add ability to break at specific kernel function

Adds a GDB callable function that sets a breakpoint at
the beginning of a kernel function.
/gem5/src/mem/slicc/ast/
H A DMachineAST.py11283:4cc8b312f026 Mon Jul 20 10:15:00 EDT 2015 Tony Gutierrez <anthony.gutierrez@amd.com> ruby: slicc: have a static MachineType

This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one. The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.

The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier. This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix
11282:afdcebd314be Mon Jul 20 10:15:00 EDT 2015 Tony Gutierrez <anthony.gutierrez@amd.com> ruby: slicc: remove support for single machine, multiple types

This patch is imported from reviewboard patch 2550 by Nilay.
It was possible to specify multiple machine types with a single state machine.
This seems unnecessary and is being removed.
/gem5/src/dev/sparc/
H A Ddtod.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
/gem5/src/arch/x86/
H A Dtypes.cc10924:d02e9c239892 Fri Jul 17 12:31:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> x86: decode instructions with vex prefix

This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
/gem5/src/proto/
H A DSConscript11247:76f75db08e09 Mon Dec 07 17:42:00 EST 2015 Radhika Jagtap <radhika.jagtap@ARM.com> proto, probe: Add elastic trace probe to o3 cpu

The elastic trace is a type of probe listener and listens to probe points
in multiple stages of the O3CPU. The notify method is called on a probe
point typically when an instruction successfully progresses through that
stage.

As different listener methods mapped to the different probe points execute,
relevant information about the instruction, e.g. timestamps and register
accesses, are captured and stored in temporary InstExecInfo class objects.
When the instruction progresses through the commit stage, the timing and the
dependency information about the instruction is finalised and encapsulated in
a struct called TraceInfo. TraceInfo objects are collected in a list instead
of writing them out to the trace file one a time. This is required as the
trace is processed in chunks to evaluate order dependencies and computational
delay in case an instruction does not have any register dependencies. By this
we achieve a simpler algorithm during replay because every record in the
trace can be hooked onto a record in its past. The instruction dependency
trace is written out as a protobuf format file. A second trace containing
fetch requests at absolute timestamps is written to a separate protobuf
format file.

If the instruction is not executed then it is not added to the trace.
The code checks if the instruction had a fault, if it predicated
false and thus previous register values were restored or if it was a
load/store that did not have a request (e.g. when the size of the
request is zero). In all these cases the instruction is set as
executed by the Execute stage and is picked up by the commit probe
listener. But a request is not issued and registers are not written.
So practically, skipping these should not hurt the dependency modelling.

If squashing results in squashing younger instructions, it may happen that
the squash probe discards the inst and removes it from the temporary
store but execute stage deals with the instruction in the next cycle which
results in the execute probe seeing this inst as 'new' inst. A sequence
number of the last processed trace record is used to trap these cases and
not add to the temporary store.

The elastic instruction trace and fetch request trace can be read in and
played back by the TraceCPU.
10695:ef2c71a5f02e Mon Feb 16 03:32:00 EST 2015 Ali Saidi <Ali.Saidi@ARM.com> cpu: add support for outputing a protobuf formatted CPU trace

Doesn't support x86 due to static instruction representation.

Completed in 157 milliseconds

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