Searched hist:2015 (Results 426 - 450 of 1505) sorted by relevance

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/gem5/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/
H A Dsimerr10754:02621b4f013b Mon Mar 23 06:57:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Final reclassification of quick regressions

A few regressions were still considered long, but finished well within
the 180 seconds. They are only a handful (mostly mcf in atomic).
H A Dstats.txt11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10754:02621b4f013b Mon Mar 23 06:57:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Final reclassification of quick regressions

A few regressions were still considered long, but finished well within
the 180 seconds. They are only a handful (mostly mcf in atomic).
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/
H A Dconfig.ini11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
11066:969113566d50 Sun Aug 30 01:24:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changes.
10736:4433fb00fa7d Mon Mar 09 10:39:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes to due to recent set of patches
/gem5/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/
H A Dstats.txt11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time

This patch takes a first stab at recategorising the regression tests
based on actual run times. The simple-atomic and simple-timing runs of
vortex and twolf all finish in less than 180 s, and they are
consequently moved from long to quick. All realview64 linux-boot
regressions take more than 700 s, and they are therefore moved to
long.

Later patches will rename quick to short, and further divide the
regressions into short, medium and long.
/gem5/src/dev/virtio/
H A Dfs9p.hh11204:7a9eeecf2b52 Thu Nov 05 04:40:00 EST 2015 Sascha Bischoff <sascha.bischoff@ARM.com> dev: Add basic checkpoint support to VirtIO9PProxy device

This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts to checkpoint gem5 with a present 9P
device caused gem5 to fatal as none of the state is tracked. We still
do not track any state, but we replace the fatal with a warning which
is triggered if the device has been used by the guest system. In the
event that it has not been used, we assume that no state is lost
during checkpointing. The warning is triggered on both a serialize and
an unserialize to ensure maximum visibility for the user.
11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
H A Dblock.hh11264:dc389d2d2f79 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move storage devices to src/dev/storage/

Move the IDE controller and the disk implementations to
src/dev/storage.
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/
H A Dsimerr11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
/gem5/src/cpu/kvm/
H A Ddevice.cc10859:0ba6f47025d1 Mon Jun 01 14:44:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm, dev: Add an in-kernel GIC implementation

This changeset adds a GIC implementation that uses the kernel's
built-in support for simulating the interrupt controller. Since there
is currently no support for state transfer between gem5 and the
kernel, the device model does not support serialization and CPU
switching (which would require switching to a gem5-simulated GIC).
/gem5/src/dev/net/
H A Dpktfifo.hh11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
H A Dpktfifo.cc11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
/gem5/src/python/m5/ext/pyfdt/
H A DLICENCE12468:b4b8bdb9712a Wed Dec 16 10:43:00 EST 2015 Glenn Bergmans <glenn.bergmans@arm.com> ext: DT autogeneration - Add PyFtd to m5 space

This patch adds pyfdt.py to the m5.ext module. This is used in
succeeding patches for generating and editing dtb files and flat
device trees for DT autogeneration.

The file is in the m5_root/src/python/m5/ext directory, as opposed to
the m5_root/ext, because this library is part of the m5 object space
and linking to the m5_root/ext directory from the SConscript file
in src/python can not be done reliably. Linking from the root level
SConscript is also not an option, because it doesn't have the PySource
method defined.

Cloned from: https://github.com/superna9999/pyfdt
Commit: accbcd254584c9295a18878d32999d0c7c156f8e
Version: 0.3

Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5961
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A DREADME.md12468:b4b8bdb9712a Wed Dec 16 10:43:00 EST 2015 Glenn Bergmans <glenn.bergmans@arm.com> ext: DT autogeneration - Add PyFtd to m5 space

This patch adds pyfdt.py to the m5.ext module. This is used in
succeeding patches for generating and editing dtb files and flat
device trees for DT autogeneration.

The file is in the m5_root/src/python/m5/ext directory, as opposed to
the m5_root/ext, because this library is part of the m5 object space
and linking to the m5_root/ext directory from the SConscript file
in src/python can not be done reliably. Linking from the root level
SConscript is also not an option, because it doesn't have the PySource
method defined.

Cloned from: https://github.com/superna9999/pyfdt
Commit: accbcd254584c9295a18878d32999d0c7c156f8e
Version: 0.3

Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5961
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A D__init__.py12468:b4b8bdb9712a Wed Dec 16 10:43:00 EST 2015 Glenn Bergmans <glenn.bergmans@arm.com> ext: DT autogeneration - Add PyFtd to m5 space

This patch adds pyfdt.py to the m5.ext module. This is used in
succeeding patches for generating and editing dtb files and flat
device trees for DT autogeneration.

The file is in the m5_root/src/python/m5/ext directory, as opposed to
the m5_root/ext, because this library is part of the m5 object space
and linking to the m5_root/ext directory from the SConscript file
in src/python can not be done reliably. Linking from the root level
SConscript is also not an option, because it doesn't have the PySource
method defined.

Cloned from: https://github.com/superna9999/pyfdt
Commit: accbcd254584c9295a18878d32999d0c7c156f8e
Version: 0.3

Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5961
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/
H A Dhmc_controller.hh11184:07b0dacf27d6 Tue Nov 03 01:17:00 EST 2015 Erfan Azarkhish <erfan.azarkhish@unibo.it> mem: hmc: adds controller

This patch models a simple HMC Controller. It simply schedules the incoming
packets to HMC Serial Links using a round robin mechanism. This patch should
be applied in series with other patches modeling a complete HMC device.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/configs/learning_gem5/
H A DREADME11104:2d537040a4b9 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> config: Add configs scripts used in Learning gem5

Added a new directory in configs (learning_gem5) to hold the scripts that are
used in the book. See http://lowepower.com/jason/learning_gem5/ for a working
copy. For now, only the scripts in Part 1: Getting started with gem5
have been added. A separate patch adds tests for these scripts.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/ext/sst/
H A DExtMaster.cc11158:a84eecaaa866 Tue Oct 06 19:08:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: fix SST connector

The renamings in changesets 8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector. This commit repeats those renamings in ext/sst.
11158:a84eecaaa866 Tue Oct 06 19:08:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: fix SST connector

The renamings in changesets 8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector. This commit repeats those renamings in ext/sst.
11158:a84eecaaa866 Tue Oct 06 19:08:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: fix SST connector

The renamings in changesets 8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector. This commit repeats those renamings in ext/sst.
10779:3e986011e99e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> ext: Add SST connector

This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
/gem5/src/dev/arm/
H A Dgic_v2m.cc10749:ac3611ba911c Thu Mar 19 04:06:00 EDT 2015 Matt Evans <matt.evans@arm.com> arm: Add a GICv2m device

This patch adds a new PIO-accessible GICv2m shim. This shim has a PIO
slave port on one side, and SPI 'wires' on the other. It accepts MSIs
from the system and triggers SPIs on the GIC. It is configurable with
a number of frames, each of which has a number of SPIs and a base SPI
offset.

A Linux driver for GICv2m is available upstream.
/gem5/src/dev/storage/
H A Dide_ctrl.hh11264:dc389d2d2f79 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move storage devices to src/dev/storage/

Move the IDE controller and the disk implementations to
src/dev/storage.
/gem5/src/mem/ruby/common/
H A DIntVec.hh11210:64c0ebeae224 Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> ruby: added stl vector of ints to be used by SLICC
/gem5/configs/common/
H A DSimpleOpts.py11104:2d537040a4b9 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> config: Add configs scripts used in Learning gem5

Added a new directory in configs (learning_gem5) to hold the scripts that are
used in the book. See http://lowepower.com/jason/learning_gem5/ for a working
copy. For now, only the scripts in Part 1: Getting started with gem5
have been added. A separate patch adds tests for these scripts.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/src/cpu/
H A DCPUTracers.py10663:fae54a666162 Sun Jan 25 07:22:00 EST 2015 Ali Saidi <Ali.Saidi@ARM.com> cpu: Put all CPU instruction tracers in a single file
H A DInstPBTrace.py10695:ef2c71a5f02e Mon Feb 16 03:32:00 EST 2015 Ali Saidi <Ali.Saidi@ARM.com> cpu: add support for outputing a protobuf formatted CPU trace

Doesn't support x86 due to static instruction representation.
/gem5/src/dev/i2c/
H A DI2C.py11262:3aeb879a66e6 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move i2c functionality to src/dev/i2c/
/gem5/src/dev/pci/
H A DPciDevice.py11260:bedcc64f6145 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move existing PCI device functionality to src/dev/pci

Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.
H A DCopyEngine.py11261:2050602b55f7 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move the CopyEngine class to src/dev/pci

Completed in 61 milliseconds

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