Searched hist:2014 (Results 551 - 575 of 1681) sorted by relevance

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/gem5/tests/long/se/20.parser/ref/x86/linux/simple-atomic/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/se/00.hello/ref/power/linux/simple-atomic/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/src/arch/arm/
H A Dstage2_lookup.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
10379:c00f6d7e2681 Fri Sep 19 10:35:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Pass faults by const reference where possible

This patch changes how faults are passed between methods in an attempt
to copy as few reference-counting pointer instances as possible. This
should avoid unecessary copies being created, contributing to the
increment/decrement of the reference counters.
10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/src/cpu/minor/
H A Dfetch1.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
10379:c00f6d7e2681 Fri Sep 19 10:35:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Pass faults by const reference where possible

This patch changes how faults are passed between methods in an attempt
to copy as few reference-counting pointer instances as possible. This
should avoid unecessary copies being created, contributing to the
increment/decrement of the reference counters.
10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
H A DSConsopts10319:4207f9bfcceb Wed Sep 03 07:42:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arch, cpu: Factor out the ExecContext into a proper base class

We currently generate and compile one version of the ISA code per CPU
model. This is obviously wasting a lot of resources at compile
time. This changeset factors out the interface into a separate
ExecContext class, which also serves as documentation for the
interface between CPUs and the ISA code. While doing so, this
changeset also fixes up interface inconsistencies between the
different CPU models.

The main argument for using one set of ISA code per CPU model has
always been performance as this avoid indirect branches in the
generated code. However, this argument does not hold water. Booting
Linux on a simulated ARM system running in atomic mode
(opt/10.linux-boot/realview-simple-atomic) is actually 2% faster
(compiled using clang 3.4) after applying this patch. Additionally,
compilation time is decreased by 35%.
10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
H A Dfunc_unit.cc10417:710ee116eb68 Sat Sep 27 09:08:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use const StaticInstPtr references where possible

This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.
10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
/gem5/src/arch/arm/insts/
H A Dfplib.cc10272:336c7d36ac00 Tue Mar 11 10:50:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> arm: remove dead code fplib mul64x64
10104:ff709c429b7b Fri Mar 07 15:56:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> scons: Fixes uninitialized warnings issued by clang

Small fixes to appease recent clang versions.
10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/
H A Dstats.txt10585:1c9d5d9417b3 Tue Dec 02 06:08:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for fixes, mostly TLB and WriteInvalidate
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/
H A Dconfig.ini10517:ba51f8572571 Mon Nov 03 11:14:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update stats no match.

Bootloader I had on my sytem was an older version with a couple of
instruction differences.
10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes.
10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/
H A Dconfig.ini10517:ba51f8572571 Mon Nov 03 11:14:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update stats no match.

Bootloader I had on my sytem was an older version with a couple of
instruction differences.
10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes.
10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/src/base/
H A Ddebug.hh10360:919c02740209 Tue Sep 09 04:36:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Fix a number of unitialised variables and members

Static analysis unearther a bunch of uninitialised variables and
members, and this patch addresses the problem. In all cases these
omissions seem benign in the end, but at least fixing them means less
false positives next time round.
10171:a9be596271b7 Wed Apr 23 05:17:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> base: explicitly suggest potential use of 'All' debug flags

Without this declaration, new clangs will complain about this value
being unused. It has no explicit use in the codebase, but it can be
useful to turn on all debugging flags while in a debugger to greatly
increase simulator verbosity.
/gem5/src/mem/ruby/structures/
H A DPrefetcher.hh10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components

This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.
10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.
H A DTBETable.hh10441:5377550e1e15 Sat Oct 11 16:02:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: structures: coorect #ifndef macros in header files
10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.
/gem5/src/sim/
H A Dglobal_event.hh10361:280cc9b0794f Tue Sep 09 04:36:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> sim: Fix resource leak in BaseGlobalEvent

Static analysis revealed that BaseGlobalEvent::barrier was never
deallocated. This changeset solves this leak by making the barrier
allocation a part of the BaseGlobalEvent instead of storing a pointer
to a separate heap-allocated barrier.
10153:936a3a8006f6 Thu Apr 03 05:22:00 EDT 2014 Andreas Sandberg <andreas@sandberg.pp.se> sim: Add the ability to lock and migrate between event queues

We need the ability to lock event queues to enable device accesses
across threads. The serviceOne() method now takes a service lock prior
to handling a new event. By locking an event queue, a different
thread/eq can effectively execute in the context of the locked event
queue. To simplify temporary event queue migrations, this changeset
introduces the EventQueue::ScopedMigration class that unlocks the
current event queue, locks a new event queue, and updates the current
event queue variable.

In order to prevent deadlocks, event queues need to be released when
waiting on barriers. This is implemented using the
EventQueue::ScopedRelease class. An instance of this class is, for
example, used in the BaseGlobalEvent class to release the event queue
when waiting on the synchronization barrier.

The intended use for this functionality is when devices need to be
accessed across thread boundaries. For example, when fast-forwarding,
it might be useful to run devices and CPUs in separate threads. In
such a case, the CPU locks the device queue whenever it needs to
perform IO. This functionality is primarily intended for KVM.

Note: Migrating between event queues can lead to non-deterministic
timing. Use with extreme care!
/gem5/src/mem/slicc/symbols/
H A DTransition.py10228:1a85c4fc805c Fri May 23 07:07:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove unused ids DNUCA*
10165:7e9edf4297a9 Sat Apr 19 10:00:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: slight change to rule for transitions
It had an unnecessary pairs token which is being removed.
/gem5/tests/configs/
H A Dtgen-dram-ctrl.py10405:7a618c07e663 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.
10218:5a45f124a2f7 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> tests: Reflect name change in DRAM tests

This patch reflects the recent name change in the DRAM TrafficGen
tests and also tidies up the test directory.
/gem5/
H A D.hgignore10235:0db28826e333 Wed Jun 04 10:48:00 EDT 2014 Yasuko Eckert <yasuko.eckert@amd.com> ext: Add a McPAT regression tester
Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko
Eckert modified them to reflect the new McPAT interface and other changes
the previous patch made.
10066:06a33d872798 Tue Feb 18 05:50:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/
H A Dsimerr10411:d96740732a61 Sun Sep 21 23:04:00 EDT 2014 Steve Reinhardt <stever@gmail.com> stats: update t1000 stats for recent changes
10222:d51e31eef415 Mon May 12 17:22:00 EDT 2014 Steve Reinhardt <stever@gmail.com> tests: update t1000 & pc-switcheroo-full stats

committed reference config.json files too
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/
H A Dstats.txt10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/
H A Dsimerr10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/
H A Dstats.txt10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/
H A Dstats.txt10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes

Completed in 71 milliseconds

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