Searched hist:2014 (Results 426 - 450 of 1681) sorted by relevance
| /gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/ | ||
| H A D | bounds.py | 10474:799c8ee4ecba Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use shared_ptr for all Faults This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared". |
| /gem5/src/arch/x86/isa/insts/system/ | ||
| H A D | undefined_operation.py | 10474:799c8ee4ecba Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use shared_ptr for all Faults This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared". |
| /gem5/src/arch/x86/ | ||
| H A D | stacktrace.hh | 10417:710ee116eb68 Sat Sep 27 09:08:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use const StaticInstPtr references where possible This patch optimises the passing of StaticInstPtr by avoiding copying the reference-counting pointer. This avoids first incrementing and then decrementing the reference-counting pointer. |
| /gem5/src/cpu/checker/ | ||
| H A D | SConsopts | 10319:4207f9bfcceb Wed Sep 03 07:42:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arch, cpu: Factor out the ExecContext into a proper base class We currently generate and compile one version of the ISA code per CPU model. This is obviously wasting a lot of resources at compile time. This changeset factors out the interface into a separate ExecContext class, which also serves as documentation for the interface between CPUs and the ISA code. While doing so, this changeset also fixes up interface inconsistencies between the different CPU models. The main argument for using one set of ISA code per CPU model has always been performance as this avoid indirect branches in the generated code. However, this argument does not hold water. Booting Linux on a simulated ARM system running in atomic mode (opt/10.linux-boot/realview-simple-atomic) is actually 2% faster (compiled using clang 3.4) after applying this patch. Additionally, compilation time is decreased by 35%. |
| /gem5/src/cpu/ | ||
| H A D | exec_context.cc | 10319:4207f9bfcceb Wed Sep 03 07:42:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arch, cpu: Factor out the ExecContext into a proper base class We currently generate and compile one version of the ISA code per CPU model. This is obviously wasting a lot of resources at compile time. This changeset factors out the interface into a separate ExecContext class, which also serves as documentation for the interface between CPUs and the ISA code. While doing so, this changeset also fixes up interface inconsistencies between the different CPU models. The main argument for using one set of ISA code per CPU model has always been performance as this avoid indirect branches in the generated code. However, this argument does not hold water. Booting Linux on a simulated ARM system running in atomic mode (opt/10.linux-boot/realview-simple-atomic) is actually 2% faster (compiled using clang 3.4) after applying this patch. Additionally, compilation time is decreased by 35%. |
| H A D | timebuf.hh | 10200:1ab8753de4d8 Fri May 09 18:58:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Timebuf const accessors Add const accessors for timebuf elements. |
| /gem5/src/arch/null/ | ||
| H A D | cpu_dummy.hh | 10102:b5de69974a2e Fri Mar 07 15:56:00 EST 2014 Ali Saidi <ali.saidi@arm.com> mem: Wakeup sleeping CPUs without caches on LLSC For systems without caches, the LLSC code does not get snoops for wake-ups. We add the LLSC code in the abstract memory to do the job for us. |
| /gem5/src/dev/virtio/ | ||
| H A D | pci.hh | 10388:a26a20060ba3 Sat Sep 20 17:17:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> dev, pci: Implement basic VirtIO support This patch adds support for VirtIO over the PCI bus. It does so by providing the following new SimObjects: * VirtIODeviceBase - Abstract base class for VirtIO devices. * PciVirtIO - VirtIO PCI transport interface. A VirtIO device is hooked up to the guest system by adding a PciVirtIO device to the PCI bus and connecting it to a VirtIO device using the vio parameter. New VirtIO devices should inherit from VirtIODevice base and implementing one or more VirtQueues. The VirtQueues are usually device-specific and all derive from the VirtQueue class. Queues must be registered with the base class from the constructor since the device assumes that the number of queues stay constant. |
| /gem5/src/mem/ruby/structures/ | ||
| H A D | WireBuffer.py | 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. |
| /gem5/src/mem/slicc/ast/ | ||
| H A D | ExprStatementAST.py | 10226:056363356d15 Fri May 23 07:07:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer: drop dequeue_getDelayCycles() The functionality of updating and returning the delay cycles would now be performed by the dequeue() function itself. |
| /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/ | ||
| H A D | system.terminal | 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. |
| /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/ | ||
| H A D | system.terminal | 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. |
| /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/ | ||
| H A D | system.terminal | 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. |
| /gem5/ext/drampower/src/ | ||
| H A D | CmdScheduler.cc | 10428:0caf62b57dfd Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> ext: Add DRAMPower to enable on-line DRAM power modelling This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit 8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the simulator. We have chosen this specific version of DRAMPower as it provides the necessary functionality, and future updates will be coordinated with the DRAMPower development team. The files added only include the bits needed to build the library, thus excluding all memory specifications, traces, and the stand-alone DRAMPower command-line tool. A future patch includes the DRAMPower functionality in the DRAM controller, to enable on-line DRAM power modelling, and avoid using post-processing of traces. |
| H A D | CmdScheduler.h | 10428:0caf62b57dfd Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> ext: Add DRAMPower to enable on-line DRAM power modelling This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit 8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the simulator. We have chosen this specific version of DRAMPower as it provides the necessary functionality, and future updates will be coordinated with the DRAMPower development team. The files added only include the bits needed to build the library, thus excluding all memory specifications, traces, and the stand-alone DRAMPower command-line tool. A future patch includes the DRAMPower functionality in the DRAM controller, to enable on-line DRAM power modelling, and avoid using post-processing of traces. |
| H A D | MemCommand.cc | 10428:0caf62b57dfd Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> ext: Add DRAMPower to enable on-line DRAM power modelling This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit 8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the simulator. We have chosen this specific version of DRAMPower as it provides the necessary functionality, and future updates will be coordinated with the DRAMPower development team. The files added only include the bits needed to build the library, thus excluding all memory specifications, traces, and the stand-alone DRAMPower command-line tool. A future patch includes the DRAMPower functionality in the DRAM controller, to enable on-line DRAM power modelling, and avoid using post-processing of traces. |
| H A D | MemArchitectureSpec.h | 10428:0caf62b57dfd Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> ext: Add DRAMPower to enable on-line DRAM power modelling This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit 8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the simulator. We have chosen this specific version of DRAMPower as it provides the necessary functionality, and future updates will be coordinated with the DRAMPower development team. The files added only include the bits needed to build the library, thus excluding all memory specifications, traces, and the stand-alone DRAMPower command-line tool. A future patch includes the DRAMPower functionality in the DRAM controller, to enable on-line DRAM power modelling, and avoid using post-processing of traces. |
| H A D | MemorySpecification.h | 10428:0caf62b57dfd Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> ext: Add DRAMPower to enable on-line DRAM power modelling This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit 8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the simulator. We have chosen this specific version of DRAMPower as it provides the necessary functionality, and future updates will be coordinated with the DRAMPower development team. The files added only include the bits needed to build the library, thus excluding all memory specifications, traces, and the stand-alone DRAMPower command-line tool. A future patch includes the DRAMPower functionality in the DRAM controller, to enable on-line DRAM power modelling, and avoid using post-processing of traces. |
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/ | ||
| H A D | simerr | 10515:bd7c2aa12122 Thu Oct 30 00:50:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Add 64-bit ARM regression tests |
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/ | ||
| H A D | simerr | 10515:bd7c2aa12122 Thu Oct 30 00:50:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Add 64-bit ARM regression tests |
| /gem5/tests/long/se/10.mcf/ref/arm/linux/minor-timing/ | ||
| H A D | simerr | 10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
| /gem5/tests/long/se/30.eon/ref/arm/linux/minor-timing/ | ||
| H A D | simerr | 10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
| /gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/ | ||
| H A D | simerr | 10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
| /gem5/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/ | ||
| H A D | simerr | 10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
| /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/ | ||
| H A D | simerr | 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
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