Searched hist:2011 (Results 376 - 400 of 897) sorted by relevance
/gem5/src/arch/x86/isa/microops/ | ||
H A D | ldstop.isa | 8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands. By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things. 8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations. 8440:e513600a3551 Sun Jul 03 01:31:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Fix store microops so they don't drop faults in timing mode. If a fault was returned by the CPU when a store initiated it's write, the store instruction would ignore the fault. This change fixes that. 8432:4a0c9c9409e4 Tue Jun 21 22:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Eliminate an unused argument for building store microops. 8103:53c2d9b1c15d Wed Mar 02 01:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Mark IO reads and writes as non-speculative. 8102:77ee9ad2e113 Wed Mar 02 01:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Mark prefetches as such in their instruction and request flags. 7967:b243dc8cec8b Sun Feb 13 20:44:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Don't read in dest regs if all bits are replaced. In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or 64 bits wide overwrite all bits of the destination register. This change removes false dependencies in these cases where the previous value of a register doesn't need to be read to write a new value. New versions of most microops are created that have a "Big" suffix which simply overwrite their destination, and the right version to use is selected during microop allocation based on the selected data size. This does not change the performance of the O3 CPU model significantly, I assume because there are other false dependencies from the condition code bits in the flags register. 7874:c7f15c60898e Wed Feb 02 22:57:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of the stupd microop. |
/gem5/src/cpu/ | ||
H A D | translation.hh | 8486:c4e77a9563f5 Sun Aug 07 12:21:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Translation: Use a pointer type as the template argument. This allows regular pointers and reference counted pointers without having to use any shim structures or other tricks. 7944:1daf51f62013 Fri Feb 11 19:29:00 EST 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Enhance data address translation by supporting hardware page table walkers. Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution. |
H A D | pc_event.cc | 8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8231:51cf7f3cf9ac Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> debug: create a Debug namespace 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/dev/arm/ | ||
H A D | kmi.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7950:1120b07dd4b0 Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> VNC/ARM: Use VNC server and add support to boot into X11 |
/gem5/src/dev/mips/ | ||
H A D | malta_cchip.cc | 8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS. 8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode. |
H A D | malta_io.cc | 8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/sim/ | ||
H A D | core.cc | 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | process_impl.hh | 8766:b0773af78423 Sun Oct 30 03:32:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the base process class in FS. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
H A D | pseudo_inst.cc | 8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh. 8784:05fb20d7064b Wed Nov 02 05:11:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in sim. 8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS. 8580:a32e8ce374d6 Thu Sep 22 21:59:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> pseudo_inst: clean up workbegin/workend functions Use exitSimLoop() function instead of explicitly scheduling on mainEventQueue (which won't work once we go to multiple event queues). Also introduced a local params variable to shorten a lot of expressions. 8555:6fd8d0432d8d Mon Sep 19 02:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Pseudoinst: Add an initParam pseudo inst function. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8231:51cf7f3cf9ac Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> debug: create a Debug namespace 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. 7914:eee5bb0fb8ea Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> m5: added work completed monitoring support |
/gem5/src/arch/arm/ | ||
H A D | types.hh | 8361:641193dca496 Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> cpus/isa: add a != operator for pcstate 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8205:7ecbffb674aa Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Cleanup implementation of ITSTATE and put important code in PCState. Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. 8181:f789b9aac5f4 Sat Mar 26 09:23:00 EDT 2011 Korey Sewell <ksewell@umich.edu> mips: cleanup ISA-specific code *** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway. 8146:18368caa8489 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Identify branches as conditional or unconditional and direct or indirect. 8075:dc266f3bcae4 Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: This panic can be hit during misspeculation so it can't exist. 8074:18b2129b852d Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Bad interworking warn way to noisy when running real code w/misspeculation. 7858:ee6641d7c713 Tue Jan 18 17:30:00 EST 2011 Matt.Horsnell <Matt.Horsnell@arm.com> O3: Fix itstate prediction and recovery. Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details. |
H A D | pagetable.hh | 8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
H A D | faults.hh | 8782:10c9297e14d5 Wed Nov 02 04:25:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 8591:8f23aeaf6a91 Tue Sep 27 03:24:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Replace calls to genMachineCheckFault with M5PanicFault. 8545:a3992291e230 Tue Sep 13 00:58:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> LSQ: Only trigger a memory violation with a load/load if the value changes. Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking). This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores. The performance improvement on SPEC benchmarks can be substantial (2-10%). 8518:9c87727099ce Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> Fix bugs due to interaction between SEV instructions and O3 pipeline SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8202:1b63e9afeafc Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix table walk going on while ASID changes error 7850:02450f4443ce Tue Jan 18 17:30:00 EST 2011 Matt Horsnell <Matt.Horsnell@arm.com> O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | isa_traits.hh | 8542:7230ff0738e3 Fri Sep 09 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> StaticInst: Merge StaticInst and StaticInstBase. Having two StaticInst classes, one nominally ISA dependent and the other ISA dependent, has not been historically useful and makes the StaticInst class more complicated that it needs to be. This change merges StaticInstBase into StaticInst. 8518:9c87727099ce Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> Fix bugs due to interaction between SEV instructions and O3 pipeline SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending. 8065:5143254707ed Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Make Noop actually decode to a noop and set it's instflags. 7846:ff8e3075d762 Tue Jan 18 17:30:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Use an actual NOP instead of a instruction that happens to do nothing 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/arch/mips/ | ||
H A D | MipsSystem.py | 8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS. 8773:ac39e3421c34 Sun Oct 30 20:38:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> System: Push boot_cpu_frequency down into the subclasses that actually use it. This parameter depends on a number of coincidences to work properly. First, there must be an array assigned to system called "cpu" even though there's no parameter called that. Second, the items in the "cpu" array have to have a "clock" parameter which has a "frequency" member. This is true of the normal CPUs, but isn't true of the memory tester CPUs. This happened to work before because the memory tester CPUs were only used in SE mode where this parameter was being excluded. Since everything is being pulled into a common binary, this won't work any more. Since the boot_cpu_frequency parameter is only used by Alpha's Linux System object (and Mips's through copy and paste), the definition of that parameter is moved down to those objects specifically. |
H A D | remote_gdb.cc | 8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS. 8544:2862c39f66f8 Sat Sep 10 06:45:00 EDT 2011 Deyuan Guo <guodeyuan@tsinghua.org.cn> MIPS: Implement gem5/src/arch/mips/remote_gdb.cc. So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote debugging. Testing: Build gem5 for MIPS_SE and make gem5 wait at beginning: modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc; scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU ---- Build GDB-7.3 mips-cross: ./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/ make make install ---- Run: ./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches ./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello (gdb) target remote :7000 (gdb) info registers (gdb) disassemble (gdb) si (gdb) break main (gdb) c (gdb) quit Testing done. |
H A D | SConscript | 8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS. 8758:8c9bd68c5a55 Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Build vtophys in SE mode. 8745:575cab0db076 Sun Oct 09 03:15:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the Interrupt objects in SE mode. 8544:2862c39f66f8 Sat Sep 10 06:45:00 EDT 2011 Deyuan Guo <guodeyuan@tsinghua.org.cn> MIPS: Implement gem5/src/arch/mips/remote_gdb.cc. So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote debugging. Testing: Build gem5 for MIPS_SE and make gem5 wait at beginning: modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc; scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU ---- Build GDB-7.3 mips-cross: ./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/ make make install ---- Run: ./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches ./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello (gdb) target remote :7000 (gdb) info registers (gdb) disassemble (gdb) si (gdb) break main (gdb) c (gdb) quit Testing done. 8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags |
/gem5/src/arch/x86/ | ||
H A D | mmapped_ipr.hh | 8768:314eb1e2fa94 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of more uses of FULL_SYSTEM. 8105:906864dd0937 Wed Mar 02 02:18:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Spelling: Fix the a spelling error by changing mmaped to mmapped. There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. |
H A D | memhelpers.hh | 8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. 8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations. |
H A D | tlb.cc | 8768:314eb1e2fa94 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of more uses of FULL_SYSTEM. 8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. 8752:28e899b7dee3 Thu Oct 13 05:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Turn on the page table walker in SE mode. 8582:dd79a696b91c Fri Sep 23 05:42:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Move the MSR lookup table out of the TLB and into its own file. Translating MSR addresses into MSR register indices took a lot of space in the TLB source and made looking around in that file awkward. This change moves the lookup into its own file to get it out of the way. It also changes it from a switch statement to a hash map which should hopefully be a little more efficient. 8539:7d3ea3c65c66 Fri Sep 09 04:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Stack: Tidy up some comments, a warning, and make stack extension consistent. Do some minor cleanup of some recently added comments, a warning, and change other instances of stack extension to be like what's now being done for x86. 8535:d04ae08781e2 Mon Sep 05 05:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86,TLB: Make sure the "delayedResponse" variable is always set. When an instruction is translated in the x86 TLB, a variable called delayedResponse is passed back and forth which tracks whether a translation could be completed immediately, or if there's going to be callback that will finish things up. If a read was to the internal memory space, memory mapped registers used to implement things like MSRs, the function hadn't yet gotten to where delayedResponse was set to false, it's default. That meant that the value was never set, and the TLB could start waiting for a callback that would never come. This change simply moves the assignment to above where control can divert to translateInt(). 8534:09745e0c3dd9 Fri Sep 02 20:04:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> TLB: comments and a helpful warning. Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why. Add a little warn() to explain it a bit. Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage(). 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8105:906864dd0937 Wed Mar 02 02:18:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Spelling: Fix the a spelling error by changing mmaped to mmapped. There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | SimpleNetwork.py | 8261:39e42ccddd63 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: adjusted default endpoint bandwidth The simple network's endpoint bandwidth value is used to adjust the overall bandwidth of the network. Specifically, the ration between endpoint bandwidth and the MESSAGE_SIZE_MULTIPLIER determines the increase. By setting the value to 1000, that means the bandwdith factor specified in the links translates to the link bandwidth in bytes. Previously, it was increasing that value by 10. This patch will likely require a reset of the ruby regression tester stats. 8259:36987780169e Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: moved network config params Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to only those networks that actually use those parameters. |
/gem5/src/mem/ruby/common/ | ||
H A D | SConscript | 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. 7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTFR for ProtocolTrace |
/gem5/src/base/stats/ | ||
H A D | text.cc | 8634:8390f2d80227 Thu Dec 01 03:15:00 EST 2011 Chris Emmons <chris.emmons@arm.com> Output: Add hierarchical output support and cleanup existing codebase. 8514:57c96df312a1 Fri Aug 19 16:08:00 EDT 2011 Thomas Grass <Thomas.Grass@ARM.com> Stats: Add a sparse histogram stat object. 8296:be7f03723412 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: move code that loops over all stats into python 8243:63e849f0f341 Wed Apr 20 14:14:00 EDT 2011 Brad Danofsky <bradley.danofsky@amd.com> stats: add user settable separator string for arrayed stats Default is '::', so no visible change unless it is overridden 8230:845c8eb5ac49 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: fix up code after sorting 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7831:c1e158414648 Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> stats: Add a histogram statistic type 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/dev/x86/ | ||
H A D | i8254.hh | 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | cmos.hh | 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | cmos.cc | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices |
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