Searched hist:2007 (Results 51 - 75 of 895) sorted by relevance

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/gem5/ext/libelf/
H A Dlibelf_phdr.c4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation
H A Dlibelf_shdr.c4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation
H A Dlibelf_xlate.c4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation
H A Delf_begin.c4494:b7c909b5a5e9 Wed May 30 17:08:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Fix compiling on Solaris since Nate's libelf change

SConstruct:
export env after we've set CC/CXX
ext/libelf/SConscript:
pull in the CC/CXX variables from env. Use gm4 if it exists
ext/libelf/elf_begin.c:
ext/libelf/libelf_allocate.c:
include errno.h instead of sys/errno.h
ext/libelf/elf_common.h:
use the more standard uintX_t
ext/libelf/elf_strptr.c:
ext/libelf/elf_update.c:
include sysmacros.h on Solaris for roundup()
4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation
H A Delf_strptr.c4494:b7c909b5a5e9 Wed May 30 17:08:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Fix compiling on Solaris since Nate's libelf change

SConstruct:
export env after we've set CC/CXX
ext/libelf/SConscript:
pull in the CC/CXX variables from env. Use gm4 if it exists
ext/libelf/elf_begin.c:
ext/libelf/libelf_allocate.c:
include errno.h instead of sys/errno.h
ext/libelf/elf_common.h:
use the more standard uintX_t
ext/libelf/elf_strptr.c:
ext/libelf/elf_update.c:
include sysmacros.h on Solaris for roundup()
4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation
/gem5/src/base/
H A Dcondcodes.hh5098:65373916c468 Tue Sep 25 23:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Condition Codes: Fix the findParity function.
5092:e418877ee8cb Tue Sep 25 23:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Condition Codes: Fix type error.
4715:2c37daa0ff2e Fri Jul 20 17:54:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix function which calculates the carry flag.
4683:3b49d35562ed Tue Jul 17 16:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Create a file of functions for computing condition codes.
These haven't been very thuroughly tested, so use at your own risk.
/gem5/src/arch/mips/
H A Didle_event.hh5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Ddt_constants.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
H A DSConsopts5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/src/arch/mips/linux/
H A Dthread_info.hh5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Daligned.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dhwrpb.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dsystem.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dsign_extension.py5307:e27f5a64f459 Mon Dec 03 17:32:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Please excuse my dear Aunt Sally. (precedence bug)
5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dtranslate.py5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5165:ce7b4b8a24c5 Fri Oct 19 01:41:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the XLAT instruction.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/dev/mips/
H A DconsoleCONSOLE PANIC (looping): A A Bootcode begins ... M5 console: m5MipsAccess @ 0x% ... 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dmaltareg.h5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/configs/boot/
H A Dnetperf-stream-udp-client.rcS4454:8125c4b9e306 Tue May 15 17:39:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> hopefully the final hacky change to make the bus bridge work ok
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here

src/mem/bridge.cc:
src/mem/bridge.hh:
hopefully the final hacky change to make the bus bridge work ok
4418:aaa5828991b3 Mon Apr 30 13:08:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> add a udp stream benchmark and a udp loopback benchmark
/gem5/src/arch/x86/isa/formats/
H A Derror.isa4704:09303c75d67a Wed Jul 18 20:43:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix the panic in the "error" format for x86,
4276:f0030662ee2a Wed Mar 21 15:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.
H A Dmulti.isa4609:29b5f66fed1a Wed Jun 20 15:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Implement rip relative addressing and put in some missing loads and stores.
4575:d0017efdfa02 Thu Jun 14 16:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Implement a handful more instructions and differentiate macroops based on the operand types they expect.
4542:f6ca2384b304 Tue Jun 12 12:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Use objects to pass around output code, and fix/implement a few things.

src/arch/x86/isa/formats/multi.isa:
Make the formats use objects to pass around output code.
4535:51bf0993137e Fri Jun 08 13:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix up a potentially misleading comment.
4528:f0b19ee67a7b Fri Jun 08 12:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Big changes to use the new microcode assembler.
4371:c5003760793e Tue Apr 10 13:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworked x86 a bit
4336:bd6ab22f8e11 Wed Apr 04 10:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:

MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.
4323:13ca4002d2ac Tue Apr 03 11:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
4310:8f9d834f19bc Thu Mar 29 13:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
4278:4233cadbe3c3 Wed Mar 21 17:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Start implementing groups of instructions which do the same thing on different sets of inputs.
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dconditional_jump.py5158:8cf2433105ff Fri Oct 19 01:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implemented the jrcx instruction.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/
H A Dspecialize.isa5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work.
5151:dec27c6c2b3b Fri Oct 12 23:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Added some new versions of MOV and a new argument type tag.
4868:99d4946469a1 Sat Aug 04 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement microops and instructions that manipulate the flags register.
4865:4f4a7fe48b5b Sat Aug 04 23:17:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make fixed register operands ignore register index extensions from the REX prefix.
The only cases where this was the correct behavior are now handled with the
"B" operand type, and doing things this way was breaking some instructions,
notably a shift.
4817:4888643b143c Mon Jul 30 18:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Allow RIP relative decode on -all- memory forms of operands.
4746:7960a6867f55 Sun Jul 22 21:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the operand size reflect the size specifier on the operand tags, and implement NEG
4716:68cc9f2d4f73 Fri Jul 20 17:55:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a parameter type to read a register index from the opcode itself.
4609:29b5f66fed1a Wed Jun 20 15:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Implement rip relative addressing and put in some missing loads and stores.
4601:38c989d15fef Wed Jun 20 11:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.
H A Dmain.isa4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
4544:3a64c2c0f8e9 Tue Jun 12 12:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix up a comment that wasn't changed over to x86.
4538:7665c5ecf99b Fri Jun 08 14:41:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix another outdated comment.
4533:126c53d7644a Fri Jun 08 13:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Clean up where files are included, and get rid of some cruft.

src/arch/x86/isa/main.isa:
Clean up where files are included.
4528:f0b19ee67a7b Fri Jun 08 12:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Big changes to use the new microcode assembler.
4519:f8da6b45573f Mon Jun 04 11:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking x86's microcode system. This is a work in progress, and X86 doesn't compile.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system
4348:5c21bdb46e6d Fri Apr 06 12:55:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa
4343:3f11bcf873b3 Fri Apr 06 12:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
4336:bd6ab22f8e11 Wed Apr 04 10:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:

MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.
4309:47807357f0d7 Thu Mar 29 13:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a microcode assembler. A microcode "program" is a series of statements. Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
/gem5/src/arch/
H A Dmicro_asm_test.py4509:cb4aa1952ea4 Thu May 31 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a second section to make sure the ROM is extended properly.
4507:487b70cfd58d Thu May 31 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Do something with ROM based macroops
4503:0f812a876221 Thu May 31 16:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make directives take parameters and use the directive function and not it's name
4502:766acd3fa962 Thu May 31 16:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Handle comments
4483:1e62824dcc3d Thu May 31 09:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Early micro assembler

src/arch/micro_asm.py:
Micro assembler
src/arch/micro_asm_test.py:
Test script for the micro assembler. This probably should go somewhere else eventually.
H A Dmicro_asm.py5039:a9367ed7ca7b Sat Sep 01 01:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Microassembler: Pass the actual mnemonic used to the macroop add_micro function
5009:78d53ea88c74 Sun Aug 26 23:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the microassembler accept lines which are just labels.
The labels on these lines will be associated with whatever the next microop
is.
4613:7f670817a86c Thu Jun 21 11:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix a problem where part of a microops parameters might be interpretted as an "ID", and also added support for symbols.
4603:a120ca8d8fe8 Wed Jun 20 15:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Comment out some unnecessary debug statements.
4591:f275f155962a Tue Jun 19 13:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make an error message a little more descriptive.
4566:a0ec2dee1a1b Thu Jun 14 09:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix up param regular expression to not duplicated the escaping \ and to pair up \s correctly.
4512:cfa340f9d12a Fri Jun 01 12:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Clean things up
4508:837161d544c3 Thu May 31 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add rom based macroops into the macroop dict instead of dropping them on the floor
4507:487b70cfd58d Thu May 31 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Do something with ROM based macroops
4503:0f812a876221 Thu May 31 16:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make directives take parameters and use the directive function and not it's name

Completed in 58 milliseconds

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