Searched hist:2007 (Results 476 - 500 of 895) sorted by relevance
/gem5/src/mem/cache/ | ||
H A D | SConscript | 5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all. 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. 4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
/gem5/src/python/m5/ | ||
H A D | main.py | 4850:434e8d79de49 Thu Aug 02 14:59:00 EDT 2007 Nathan Binkert <nate@binkert.org> main: expose the build information as a simple command line parameter 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. 4123:9c80390ea1bb Sat Mar 03 01:24:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Factor code out of main.cc and main.i into a bunch of files so things are organized in a more sensible manner. Take apart finalInit and expose the individual functions which are now called from python. Make checkpointing a bit easier to use. 4087:ad2f343e3d45 Wed Feb 21 17:08:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Fix tracing so it starts right away if --trace-start is not specified. 4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it. 4074:f2c4afa8cd46 Sat Feb 17 23:32:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Default to tracing being disabled in C++, it will be turned on in python. Fix the trace start code so it actually starts when it is suppsed to. Make the Exec tracing stuff obey the trace enabled flag. 4054:3d617b3be4fa Tue Feb 13 03:59:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Merge all of the execution trace configuration stuff into the traceflags infrastructure. InstExec is now just Exec and all of the command line options are now trace options. 4053:ee914b22709e Tue Feb 13 03:16:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Rearrange traceflags.py so that the file generation only happens if the script is invoked as main. This allows us to import traceflags.py if we just want the list of available flags. Embed traceflags.py into the zipfile so it can be accessed from the python side of things. With this, print an error on invalid flags and add --trace-help option that will print out the list of trace flags that are compiled in. If a flag is prefixed with a '-', now that flag will be disabled. 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. 4044:204fd77bae19 Fri Feb 09 19:30:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up from my last commit to the trace stuff. |
/gem5/src/mem/ | ||
H A D | mem_object.hh | 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4190:5069dfa3d62e Thu Mar 08 18:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> stop m5 from leaking like a sieve don't create a new physPort/virtPort every time activateContext() is called add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs() on the port owner as well as delete it's peer still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic src/cpu/thread_state.cc: if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it src/mem/bus.cc: src/mem/bus.hh: add ability to delete a port by usig a hash_map instead of an array to store port ids add a function to do deleting src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/mem_object.cc: src/mem/mem_object.hh: adda function to delete port references from a memory object src/mem/port.cc: src/mem/port.hh: add a removeConn function that tell the owener to delete any references to the port and then deletes its peer |
H A D | packet.cc | 5012:c0a28154d002 Mon Aug 27 00:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge with head 4986:b7c82ad6b3ef Fri Aug 24 16:39:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Mem: Make errors in the memory system be responses, not requests. Fixes cache handling of error responses. 4921:bcf49547dae7 Fri Jul 27 03:46:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> packet: get rid of unused intersect() function. 4880:4de4d072e977 Mon Jul 02 12:26:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix a couple LL/SC bugs that only affected timing mode. src/cpu/simple/timing.cc: Fix swap/stq_c command bug. src/mem/packet.cc: Fix incorrect LoadLockedReq command response field. 4874:cdae9adbd276 Sat Jun 30 20:51:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of obsolete fixPacket() functions. Handled by Packet::checkFunctional() now. 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4628:17b3ce796176 Thu Jun 21 14:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Getting closer... configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. 4626:ed8aacb19c03 Sun Jun 17 20:27:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> More major reorg of cache. Seems to work for atomic mode now, timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. 4622:f681e10844f3 Mon May 28 11:13:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 4489:381fcb5b6c31 Mon May 28 11:04:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Reformat comments to meet line length restriction. |
/gem5/src/cpu/o3/ | ||
H A D | SConscript | 5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all. 4497:17e34dbcc8b3 Wed May 30 20:19:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Fix cut-n-pasto to make the path correct 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. 4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
H A D | FUPool.py | 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. |
/gem5/configs/boot/ | ||
H A D | devtime.rcS | 4452:9dfce80039cd Mon May 14 16:37:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> couple more bug fixes for intel nic src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: couple more bug fixes |
/gem5/src/cpu/ | ||
H A D | func_unit.hh | 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) |
H A D | nativetrace.hh | 5049:16a0724434b8 Wed Sep 05 02:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm. 5038:c996bb7f1a6d Fri Aug 31 16:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get x86 to compile again after the simobject constructor change. 4830:aad1410a2b79 Wed Aug 01 03:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize the native tracing code. Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat. 4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. |
H A D | intr_control.cc | 5218:9b99318ca70d Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Interrupts: Inline some code and remove duplication. 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore |
/gem5/src/dev/mips/ | ||
H A D | malta_cchip.hh | 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
H A D | Malta.py | 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
/gem5/src/arch/alpha/ | ||
H A D | pagetable.cc | 5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. |
H A D | faults.hh | 5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4695:a63378aed062 Wed Jul 18 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make name, isMachineCheckFault, and isAlignmentFault const. 4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures. |
H A D | locked_mem.hh | 4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 4050:cf1daaef9109 Mon Feb 12 13:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem src/cpu/simple/atomic.cc: merge steve's changes in. 4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata 4027:53292b42ee1c Mon Feb 12 12:26:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Move store conditional result checking from SimpleAtomicCpu write function into Alpha ISA description. write now just generically returns a result value if the res pointer is non-null (which means we can only provide a res pointer if we expect a valid result value). |
H A D | idle_event.cc | 4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg |
/gem5/src/sim/ | ||
H A D | simulate.hh | 4123:9c80390ea1bb Sat Mar 03 01:24:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Factor code out of main.cc and main.i into a bunch of files so things are organized in a more sensible manner. Take apart finalInit and expose the individual functions which are now called from python. Make checkpointing a bit easier to use. |
H A D | main.cc | 5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). 4941:595b53060bc1 Sat Aug 04 19:00:00 EDT 2007 Nathan Binkert <nate@binkert.org> main: return an an exit code of 1 when we exit due to a python exception. This requires us to not use PyRun_SimpleString, but PyRun_String since the latter actually returns a result 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. 4128:5f4ef6ceb5c4 Sat Mar 03 00:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> include signal.h 4123:9c80390ea1bb Sat Mar 03 01:24:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Factor code out of main.cc and main.i into a bunch of files so things are organized in a more sensible manner. Take apart finalInit and expose the individual functions which are now called from python. Make checkpointing a bit easier to use. 4081:80f1e833d118 Sun Feb 18 12:31:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the stand alone ParamContext since all of the relevant stuff has now been moved to python. 4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it. 4073:62f6ab072e2e Sat Feb 17 23:27:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Pass an exception from a python event through the event queue back into python so we don't just silently ignore those errors 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/src/arch/mips/isa/formats/ | ||
H A D | util.isa | 5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". 4056:f8f1dffc5913 Tue Feb 13 11:09:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Update MIPS ISA description to work with new write result interface for store conditional. |
H A D | control.isa | 5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers 5224:0e354459fb8a Wed Nov 14 06:24:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". |
/gem5/src/dev/sparc/ | ||
H A D | t1000.cc | 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4000:9bf49767a9e4 Tue Jan 30 18:25:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make SPARC checkpointing work src/arch/sparc/floatregfile.cc: Fix serialization for fpreg src/arch/sparc/intregfile.cc: fix serialization for intreg src/arch/sparc/miscregfile.cc: fix serialization from miscreg src/arch/sparc/pagetable.cc: fix serialization for page table src/arch/sparc/regfile.cc: need to serialize nnpc src/arch/sparc/tlb.cc: write serialization code for tlb src/cpu/base.cc: provide a way to find the thread number a context is serialize the instruction counter src/cpu/base.hh: provide a way to find the thread number a context is and given a thread number find a context pointer src/cpu/cpuevent.hh: provide method to get thread context from a cpu event for serialization src/dev/sparc/t1000.cc: src/dev/sparc/t1000.hh: nothing to serialize in t1000 src/sim/serialize.cc: src/sim/serialize.hh: Make findObj() work (it hasn't since we did the python conversion stuff) 3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc |
/gem5/configs/splash2/ | ||
H A D | run.py | 5256:723d4c11ac26 Thu Nov 15 00:58:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Configs: Fix for benchmarks that don't use getopt. 5255:79825caee5fd Thu Nov 15 03:51:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Config: Fix some errors in the splash2 config file. 4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object. 4403:824f7311059c Mon Apr 23 16:03:00 EDT 2007 Ron Dreslinski <rdreslin@umich.edu> Fix the splash2 run script |
/gem5/src/arch/sparc/ | ||
H A D | faults.hh | 5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4695:a63378aed062 Wed Jul 18 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make name, isMachineCheckFault, and isAlignmentFault const. 4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures. 4129:702776ad560a Sat Mar 03 19:03:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem 4111:65fffcb4fae9 Wed Feb 28 11:36:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running. 4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore 3893:e2a358430839 Mon Jan 08 18:07:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion. src/arch/sparc/faults.cc: 1) s/Resumeable/Resumable/gc 2) s/if(/if (/gc 3) keep variables lowercase 4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv). src/arch/sparc/faults.hh: s/Resumeable/Resumable/ src/arch/sparc/isa_traits.hh: This is unused and unnecessary. src/arch/sparc/miscregfile.hh: add bitfield masks for some important ASRs (HPSTATE, PSTATE). 3890:5530906ab80a Fri Jan 05 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> set the softint appropriately on an timer compare interrupt there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.cc: there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.hh: correct protection defines src/arch/sparc/ua2005.cc: set the softint appropriately on an timer compare interrupt |
/gem5/src/arch/x86/ | ||
H A D | utility.cc | 5299:e61b9f2a9732 Sun Dec 02 02:09:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move startup code to the system object to initialize a Linux system. 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. 5289:ca5390e654b8 Sun Dec 02 02:00:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate the effective seg base and the "hidden" seg base. 5264:f290df2f2261 Fri Nov 16 17:18:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix 32 bit compilation. 5234:55e0b1585b04 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the startupCPU function. 5182:9032bb4332eb Tue Oct 23 20:40:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix X86_FS compilation. 5141:a3b0e3a8b83c Sun Oct 07 21:20:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make x86 initialize more state. 5135:6ae576eada5c Sun Oct 07 21:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make initCPU and startupCPU do something basic. 5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile. |
/gem5/src/base/loader/ | ||
H A D | elf_object.cc | 5152:20fc3ce35147 Fri Oct 12 23:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Loader: Identify sections based on virtual addresses, and set the LoadAddrMask correctly for x86. 5143:4207b1d8b161 Tue Oct 09 16:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> ELF Loader: Use physical addresses instead of virtual ones. This works in SE mode because the virtual and physical addresses specified for segments are the same. In Alpha, the LoadAddrMask is still necessary because the virtual and physical addresses are the same and apparently rely on the super page mechanism. All of the regressions pass. 5090:ac0d2ccc9c3b Tue Sep 25 23:03:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Loader: Load all segments of an elf, rather than just the "text" and "data". 5070:3d6a1e37b944 Tue Sep 11 00:01:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Loader: Error if a TLS section is found in the binary. 4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace it with FreeBSD's implementation 4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it. src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. 4111:65fffcb4fae9 Wed Feb 28 11:36:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running. 3925:08252e3cb1c0 Mon Jan 22 21:45:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> we decided to check for .interp instead of .dynamic 3917:a6cc1842f529 Mon Jan 22 16:14:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> check if an executable is dynamic and die if it is Only implemented for ELf. Someone might want to implement it for ecoff and some point src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.cc: src/base/loader/object_file.hh: add a function to check if an executable is dynamic src/sim/process.cc: check if an executable is dynamic and die if it is |
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