Searched hist:2007 (Results 301 - 325 of 895) sorted by relevance

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/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/
H A Dconvert_floating_point_to_gpr_integer.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/
H A Dexclusive_or.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/
H A Dmultiplication.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/compare/
H A Dcompare_and_write_minimum_or_maximum.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/data_conversion/
H A Dconvert_gpr_integer_to_floating_point.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/shift/
H A Dleft_logical_shift.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dright_logical_shift.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/
H A Dmultiplication.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/compare/
H A Dcompare_and_write_minimum_or_maximum.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/arithmetic/
H A Daddition.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dchange_sign.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dpartial_remainder.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dsubtraction.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/control/
H A Dsave_and_restore_x87_control_word.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/
H A Dexchange.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/cpu/
H A DIntrControl.py4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/
H A Dmove.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/dev/sparc/
H A Ddtod.hh4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
3990:6a5fd06c76a0 Mon Jan 29 19:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> timegm() is a gnuism... replace with the code from the timegm() man page
3943:68e673d2db04 Sun Jan 28 13:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Stick the conversion of python to unix time with all of
the other param code so that other functions can use it
as well.
3914:e83101d984d5 Sun Jan 21 18:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add dumb time of day device
/gem5/src/arch/x86/insts/
H A Dmicrofpop.cc5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
/gem5/src/arch/x86/
H A Demulenv.cc4863:b6dacc9a39ff Sat Aug 04 23:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
4848:25a45e79f9ea Thu Aug 02 18:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix special case with SIB index register and REX prefix.
4712:79b4c64296ce Thu Jul 19 18:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> x86 fixes
Make the emulation environment consider the rex prefix.
Implement and hook in forms of j, jmp, cmp, syscall, movzx
Added a format for an instruction to carry a call to the SE mode syscalls system
Made memory instructions which refer to the rip do so directly
Made the operand size overridable in the microassembly
Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on
Added an explicit "rax" operand for the syscall format
Implemented syscall returns.
4604:3ffdd00e6c02 Wed Jun 20 15:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Forgot to check these in...
H A Disa_traits.hh5228:b08c9c42907a Thu Nov 08 21:51:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.
5152:20fc3ce35147 Fri Oct 12 23:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Loader: Identify sections based on virtual addresses, and set the LoadAddrMask correctly for x86.
5127:478b14ffee54 Thu Oct 04 03:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix the PageShift constant in isa_traits.hh (I thought I alread did this?)
5121:a5f3cfdc4ee5 Wed Oct 03 01:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix x87 floating point stack register indexing.
5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile.
5082:82dd253231c8 Wed Sep 19 21:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in the foundation for x87 stack based fp registers.
5063:8eb72b1bd3c6 Thu Sep 06 19:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Rework the multiplication microops so that they work like they would in the patent.
4812:c77e159a5633 Mon Jul 30 16:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make sure FP_Base_DepTag is big enough to avoid trouble.
4772:f08370a81812 Fri Jul 27 01:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix argument register indexing.
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.
4587:2c9a2534a489 Tue Jun 19 10:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
H A Dfaults.hh5237:6c819dbe8045 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Work on the page table walker, TLB, and related faults.
5139:2422708d4fcb Sun Oct 07 21:17:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make faults maintain an error code which gets pushed on the stack.
5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
5114:edcdf9b908ec Wed Oct 03 01:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add classes for the actual x86 faults.
5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
4729:99800622a6e8 Fri Jul 20 21:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the "name" function const.
4365:f780e9fad124 Tue Apr 10 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix up the base x86 fault object and create a fault to be generated by unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.
4150:642840fd4652 Mon Mar 05 11:07:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Added fault generation functions. I would still like to see these go away. The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures.
4139:385be08269d7 Mon Mar 05 09:47:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Added a missing include.
4135:58a8bd096de9 Sun Mar 04 19:20:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Stub x86 Fault class which just panics.
/gem5/src/kern/linux/
H A Dprintk.hh4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4429:74351f86f49a Tue May 01 18:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name:
printing and the actual formatted string being printed
/gem5/src/python/m5/internal/
H A D__init__.py4859:97c7749896a6 Fri Aug 03 01:50:00 EDT 2007 Nathan Binkert <nate@binkert.org> python: Improve support for python calling back to C++ member functions.
Add support for declaring SimObjects to swig so their members can be wrapped.
Make sim_object.i only contain declarations for SimObject.
Create system.i to contain declarations for System.
Update python code to properly call the C++ given the new changes.
4382:b35e75e1b890 Fri Apr 13 00:20:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Completely re-work how the scons framework incorporates swig
and python code into m5 to allow swig an python code to
easily added by any SConscript instead of just the one in
src/python. This provides SwigSource and PySource for
adding new files to m5 (similar to Source for C++). Also
provides SimObject for including files that contain SimObject
information and build the m5.objects __init__.py file.
/gem5/src/sim/
H A Dasync.hh4123:9c80390ea1bb Sat Mar 03 01:24:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Factor code out of main.cc and main.i into a bunch of files
so things are organized in a more sensible manner. Take apart
finalInit and expose the individual functions which are now
called from python. Make checkpointing a bit easier to use.
4073:62f6ab072e2e Sat Feb 17 23:27:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Pass an exception from a python event through the event queue
back into python so we don't just silently ignore those errors

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