Searched hist:2007 (Results 201 - 225 of 895) sorted by relevance

1234567891011>>

/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/
H A Dsum_of_absolute_differences.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/compare/
H A Dcompare_and_write_mask.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/
H A Ddata_conversion.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dexit_media_state.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/
H A Dextract_and_insert.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dshuffle_and_swap.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/
H A Dmove_mask.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/
H A Dexclusive_or.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dpor.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/shift/
H A Dleft_logical_shift.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dright_arithmetic_shift.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dright_logical_shift.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/arithmetic/
H A Ddivision.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dmultiplication.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/
H A Dmicroasm.isa5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5291:5d38610cff05 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lgdt instruction.
5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work.
5232:d3801ea2792e Mon Nov 12 17:37:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Various fixes to indexing segmentation related registers
5161:e7334f2d7bef Fri Oct 19 01:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the in/out instructions. These will still need support from the TLB and memory system.
5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
5121:a5f3cfdc4ee5 Wed Oct 03 01:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix x87 floating point stack register indexing.
5082:82dd253231c8 Wed Sep 19 21:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in the foundation for x87 stack based fp registers.
5045:bf06c4d63bf4 Wed Sep 05 02:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add floating point micro registers.
5029:68c3f3be8c8a Wed Aug 29 23:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the movlpd instruction.
/gem5/src/arch/mips/
H A Dvtophys.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dvtophys.cc5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A DMipsTLB.py5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5224:0e354459fb8a Wed Nov 14 06:24:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
/gem5/src/arch/x86/isa/formats/
H A Dstring.isa5163:f08b480df4c3 Fri Oct 19 01:40:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the "fault" microop predicated.
5125:62bd932bcb0b Wed Oct 03 02:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Distinguish between the rep and repe prefixes.
STOS and MOVS only accept the rep prefix which always loops until rcx becomes
0. The other string instructions accept repe (same encoding as rep) and repne
which also check the condition code flags each iteration.
4952:2d7c40dd10bd Tue Aug 07 18:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add a format to handle string instructions which can use the repe and repne prefixes.
H A Dformats.isa4952:2d7c40dd10bd Tue Aug 07 18:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add a format to handle string instructions which can use the repe and repne prefixes.
4712:79b4c64296ce Thu Jul 19 18:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> x86 fixes
Make the emulation environment consider the rex prefix.
Implement and hook in forms of j, jmp, cmp, syscall, movzx
Added a format for an instruction to carry a call to the SE mode syscalls system
Made memory instructions which refer to the rip do so directly
Made the operand size overridable in the microassembly
Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on
Added an explicit "rax" operand for the syscall format
Implemented syscall returns.
4343:3f11bcf873b3 Fri Apr 06 12:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
4323:13ca4002d2ac Tue Apr 03 11:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
4278:4233cadbe3c3 Wed Mar 21 17:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Start implementing groups of instructions which do the same thing on different sets of inputs.
4276:f0030662ee2a Wed Mar 21 15:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.
4158:a3fb9e29c6ce Mon Mar 05 11:16:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Stub decoder. This is probably even farther from finished than it looks...
/gem5/src/arch/x86/isa/insts/general_purpose/flags/
H A Dpush_and_pop.py5176:43fb805e1b85 Sun Oct 21 21:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start using the stupd microop, and update statistics accordingly.
5174:73a760aa0129 Fri Oct 19 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dmove_string.py5125:62bd932bcb0b Wed Oct 03 02:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Distinguish between the rep and repe prefixes.
STOS and MOVS only accept the rep prefix which always loops until rcx becomes
0. The other string instructions accept repe (same encoding as rep) and repne
which also check the condition code flags each iteration.
5112:fccb2f791196 Wed Oct 03 01:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MOVS
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dstore_string.py5125:62bd932bcb0b Wed Oct 03 02:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Distinguish between the rep and repe prefixes.
STOS and MOVS only accept the rep prefix which always loops until rcx becomes
0. The other string instructions accept repe (same encoding as rep) and repne
which also check the condition code flags each iteration.
5111:65afc8009c08 Wed Oct 03 01:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement STOS.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/microops/
H A Dmicroops.isa5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
4561:ade4960f0832 Wed Jun 13 14:05:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move load/store microops into their own file. They still don't do anything, though.
4524:f051dcff22b3 Mon Jun 04 15:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make limm (load immediate) microop
4519:f8da6b45573f Mon Jun 04 11:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking x86's microcode system. This is a work in progress, and X86 doesn't compile.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system
4372:14d42d795242 Tue Apr 10 13:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Include the new GenFault microop.
4338:24d31b35bcf9 Wed Apr 04 19:35:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.

1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
Implemented polymorphic microops and changed around the microcode assembler syntax.
4298:a92aab35e34e Thu Mar 29 03:49:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add code to generate register and immediate based integer op microop classes.
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dstack_operations.py5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5179:9ea5593e01f2 Mon Oct 22 17:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Use the cda microop where appropriate. The ENTER instruction still needs these.
5176:43fb805e1b85 Sun Oct 21 21:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start using the stupd microop, and update statistics accordingly.
5175:ee904e392de2 Sun Oct 21 21:44:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the stupd microop ("store with update", not "stupid") and use it in ENTER.
5171:eab735dc951d Fri Oct 19 18:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the ENTER instruction. This could probably be optimized by cleaning up the indexing in the main loop.
5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.

Completed in 63 milliseconds

1234567891011>>