Searched hist:2007 (Results 151 - 175 of 895) sorted by relevance

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/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/
H A D__init__.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dconditional_move.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dconvert_and_load_or_store_bcd.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dextract.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/load_constants/
H A D__init__.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/
H A Dno_operation.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/stack_management/
H A D__init__.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dclear_state.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dstack_control.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/
H A D__init__.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/
H A Doutputblock.isa4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
H A Dbitfields.isa4801:370cc342f031 Mon Jul 30 16:17:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add a bitfield to indicate whether or not an REX prefix was present.
4717:040769cb51b9 Fri Jul 20 17:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a bitfield to decode based on what prefixes are used.
4586:597006d41ca8 Tue Jun 19 10:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a stack size bitfield and expose the mode component of the ExtMachInst.
4546:71382cde8725 Tue Jun 12 12:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Flesh out the bitfields for prefixes.
4541:da1910a0d731 Tue Jun 12 12:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add an address size bitfield to the isa description and the ExtMachInst
4526:4458edb6990d Fri Jun 08 12:06:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a bitfield to refer to the opSize member of the extMachInst.
4276:f0030662ee2a Wed Mar 21 15:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.
4158:a3fb9e29c6ce Mon Mar 05 11:16:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Stub decoder. This is probably even farther from finished than it looks...
/gem5/util/
H A DSConscript4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
H A Dvalgrind-suppressions4897:41b298e2bed2 Sun Jul 15 23:30:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Add valgrind-suppressions file.
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dbit_test.py5306:79cedb731af5 Sun Dec 02 04:46:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make sure the memory index is calculated using the address size for bit test instructions.
5305:8b379ad9406d Sun Dec 02 04:46:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register.
5297:4e2607ff906f Sun Dec 02 02:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix a copy paste error in the bts microcode.
5240:6dc723c9c6a9 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement some bit testing instructions.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dbounds.py5164:c2124685af1d Fri Oct 19 01:40:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the BOUND instruction.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/mips/
H A Dpra_constants.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
H A Didle_event.cc5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/sparc/
H A Dhandlers.hh4989:3e9d532cf998 Mon Aug 13 19:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work.
4114:6f845b792a1b Fri Mar 02 09:43:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Forgot to commit this new file last earlier.
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dload_string.py5150:4b5a97744185 Fri Oct 12 23:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implemented LODS.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/system/
H A Dundefined_operation.py5114:edcdf9b908ec Wed Oct 03 01:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add classes for the actual x86 faults.
4730:77e3e9b15e7e Fri Jul 20 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Implement UD2 and replace the place holder in the decoder.
/gem5/src/arch/x86/
H A Dstacktrace.hh4145:90fe789c9458 Mon Mar 05 09:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Filled in a stub header file for a stacktrace object. I'm still not sure what this is for, and it probably doesn't work on anything but Alpha.
4120:3e09b5d32c45 Sat Mar 03 11:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add build hooks for x86.
H A Dkernel_stats.hh5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile.
4120:3e09b5d32c45 Sat Mar 03 11:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add build hooks for x86.
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dloop.py5160:ada1b67c97ab Fri Oct 19 01:38:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the LOOP instructions.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/ext/libelf/
H A D_libelf.h4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation

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