Searched hist:14127 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/arch/arm/insts/ | ||
| H A D | misc64.hh | 14127:65faf17eea53 Tue Jul 30 06:34:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Rewrite MSR immediate instruction class MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | misc64.cc | 14127:65faf17eea53 Tue Jul 30 06:34:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Rewrite MSR immediate instruction class MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/isa/templates/ | ||
| H A D | misc64.isa | 14127:65faf17eea53 Tue Jul 30 06:34:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Rewrite MSR immediate instruction class MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | data64.isa | 14127:65faf17eea53 Tue Jul 30 06:34:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Rewrite MSR immediate instruction class MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | aarch64.isa | 14127:65faf17eea53 Tue Jul 30 06:34:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Rewrite MSR immediate instruction class MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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