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| H A D | miscregs.hh | 13019:3fa5ab820fa8 Tue Sep 04 06:44:00 EDT 2018 Anouk Van Laer <anouk.vanlaer@arm.com> arch-arm: Correction for address size in EL1&0 translation When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| H A D | table_walker.cc | 13019:3fa5ab820fa8 Tue Sep 04 06:44:00 EDT 2018 Anouk Van Laer <anouk.vanlaer@arm.com> arch-arm: Correction for address size in EL1&0 translation When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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