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/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
H A Dsystem.terminal11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/10.mcf/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/30.eon/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/70.twolf/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/src/dev/net/
H A Dtcp_iface.cc11622:0b2aaf6f5c78 Tue Sep 13 23:08:00 EDT 2016 Michael LeBeane <michael.lebeane@amd.com> dev: Exit correctly in dist-gem5
The receiver thread in dist_iface is allowed to directly exit the simulation.
This can cause exit to be called twice if the main thread simultaneously wants
to exit the simulation. Therefore, have the receiver thread enqueue a request
to exit on the primary event queue for the main simulation thread to handle.
/gem5/src/arch/x86/insts/
H A Dmicroop.cc10835:d4b162a57400 Fri May 15 13:39:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Appease gcc 5.1

Three minor issues are resolved:

1. Apparently gcc 5.1 does not like negation of booleans followed by
bitwise AND.

2. Somehow the compiler also gets confused and warns about
NoopMachInst being unused (removing it causes compilation errors
though). Most likely a compiler bug.

3. There seems to be a number of instances where loop unrolling causes
false positives for the array-bounds check. For now, switch to
std::array. Potentially we could disable the warning for newer gcc
versions, but switching to std::array is probably a good move in
any case.
/gem5/src/cpu/kvm/
H A DKvmVM.py9651:f551c8ad12a5 Mon Apr 22 13:20:00 EDT 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> kvm: Basic support for hardware virtualized CPUs

This changeset introduces the architecture independent parts required
to support KVM-accelerated CPUs. It introduces two new simulation
objects:

KvmVM -- The KVM VM is a component shared between all CPUs in a shared
memory domain. It is typically instantiated as a child of the
system object in the simulation hierarchy. It provides access
to KVM VM specific interfaces.

BaseKvmCPU -- Abstract base class for all KVM-based CPUs. Architecture
dependent CPU implementations inherit from this class
and implement the following methods:

* updateKvmState() -- Update the
architecture-dependent KVM state from the gem5
thread context associated with the CPU.

* updateThreadContext() -- Update the thread context
from the architecture-dependent KVM state.

* dump() -- Dump the KVM state using (optional).

In order to deliver interrupts to the guest, CPU
implementations typically override the tick() method and
check for, and deliver, interrupts prior to entering
KVM.

Hardware-virutalized CPU currently have the following limitations:
* SE mode is not supported.
* PC events are not supported.
* Timing statistics are currently very limited. The current approach
simply scales the host cycles with a user-configurable factor.
* The simulated system must not contain any caches.
* Since cycle counts are approximate, there is no way to request an
exact number of cycles (or instructions) to be executed by the CPU.
* Hardware virtualized CPUs and gem5 CPUs must not execute at the
same time in the same simulator instance.
* Only single-CPU systems can be simulated.
* Remote GDB connections to the guest system are not supported.

Additionally, m5ops requires an architecture specific interface and
might not be supported.
/gem5/tests/configs/
H A Do3-timing-checker.py9381:ffec48040ac1 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> tests: Always specify memory mode in every test system.

Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.
9311:227d19399b51 Thu Oct 25 13:14:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> config: Use SimpleDRAM in full-system, and with o3 and inorder

This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
9036:6385cf85bf12 Thu May 31 13:30:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.
8931:7a1dfb191e3f Fri Apr 06 13:46:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.
/gem5/src/dev/virtio/
H A DSConscript11930:2d22a73fa4c7 Mon Nov 07 13:14:00 EST 2016 Andreas Sandberg <andreas.sandberg@arm.com> dev: Rename VirtIO PCI debug flag

Rename VIOPci -> VIOIface to avoid having a separate flag for the MMIO
interface.

Change-Id: I99f9210fa36ce33662c48537fd3992cd9a69d349
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2324
Reviewed-by: Weiping Liao <weipingliao@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/
H A Dsimerr11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/
H A Dsimerr11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/
H A Dsimerr11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/
H A Dsimerr11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/
H A Dsimerr11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/
H A Dsimerr11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.

Completed in 71 milliseconds

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